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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt83vl38 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator august 2010 rev. 1.0.1 general description the xrt83vl38 is a fully integrated octal (eight channel) long-haul and short-haul line interface unit for t1 (1.544mbps) 100 ? , e1 (2.048mbps) 75 ? or 120 ??? j1 110 ?? or bits timing applications. in long-haul applications the xrt83vl38 accepts signals that have been attenuated from 0 to 36db at 772khz in t1 mode (equivalent of 0 to 6000 feet of cable loss) or 0 to 43db at 1024khz in e1 mode. in t1 applications, the xrt83vl38 can generate five transmit pulse shapes to meet the short-haul digital cross-connect (dsx-1) template requirements as well as for channel service units (csu) line build out (lbo) filters of 0db, -7.5db -15db and -22.5db as required by fcc rules. it also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions (the arbitrary pulse generators are available in both t1 and e1 modes). the xrt83vl38 provides both a parallel/serial host microprocessor interface as well as a hardware mode for programming and control. both the b8zs and hdb3 encoding and decoding functions are selectable as well as ami. two on-chip crystal-less jitter attenuators with a 32 or 64 bit fifo can be placed in the receive and the transmit paths with loop bandwidths of less than 3hz. the xrt83vl38 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. it supports internal impedance matching for 75 ??? 100 ??? 110 ?? and 120 ? for both transmitter and receiver. in the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications the chip includes an integrated programmable clock multiplier that can synthesize t1 or e1 master. applications ? bits timing ? t1 digital cross-connects (dsx-1) ? isdn primary rate interface ? csu/dsu e1/t1/j1 interface ? t1/e1/j1 lan/wan routers ? public switching syst ems and pbx interfaces ? t1/e1/j1 multiplexer and channel banks features (see page 2) f igure 1. b lock d iagram of the xrt83vl38 t1/e1/j1 liu (h ost m ode ) one of eight channels, channel_n - (n= 0:7) hw/host wr_r/w rd_ds ale_as cs rdy_dtack int ict tpos_n/tdata_n tneg_n/codes_n tclk_n rclk_n rneg_n/lcv_n rpos_n/rdata_n rlos_n rtip_n rring_n master clock synthesizer qrss pattern generator dmo_n ttip_n tring_n txon_n hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver drive monitor local analog loopback remote loopback digital loopback hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector network loop detector rx equalizer equalizer control ais detector los detector lbo[3:0] loopback enable ja select nlcd enable qrss enable ? pts1 ? pts2 d[7:0] ? pclk a[7:0] reset microprocessor controller test dfm taos enable mclke1 mclkt1 mclkout
xrt83vl38 2 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 features ? supports section 13 - synchronization interface in itu g.703 for both transmit and receive paths ? fully integrated eight channel long-haul or short-haul transceivers for e1,t1 or j1 applications ? adaptive receive equalizer for up to 36db cable attenuation ? programable transmit pulse shaper for e1,t1 or j1 short-haul interfaces ? five fixed transmit pulse settings for t1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shap ing available for both t1 and e1 modes ? transmit line build-outs (lbo) for t1 long-haul app lication from 0db to -22.5db in three 7.5db steps ? selectable receiver sensitivity from 0 to 36db cable loss for t1 @772khz and 0 to 43db for e1 @1024khz ? receive monitor mode handles 0 to 29db resistive at tenuation along with 0 to 6db of cable attenuation for e1 and 0 to 3db of cable attenuation for t1 modes ? supports 75 ?? and 120 ?? (e1), 100 ? (t1) and 110 ? (j1) applications ? internal and/or external impedance matching for 75 ? , 100 ??? 110 ? and 120 ? ? tri-state transmit ou tput and receive input capab ility for redundanc y applications ? provides high impedance for tx and rx during power off ? transmit return loss meets or exceeds etsi 300-166 standard ? on-chip digital clock recovery circ uit for high input jitter tolerance ? crystal-less digital jitter attenuator with 32-bit or 64-bit fifo selectable in transmit or receive paths ? on-chip frequency multiplier generates t1 or e1 master clocks ? high receiver interference immunity ? on-chip transmit short-circuit protection and limiting, and driver fa il monitor output (dmo) f igure 2. b lock d iagram of the xrt83vl38 t1/e1/j1 liu (h ardware m ode ) one of eight channels, channel_n - (n=0 : 7) hw/host gauge jasel1 jasel0 rxtsel txtsel tersel1 tersel0 rxres1 rxres0 ict mclke1 mclkt1 clksel[2:0] tpos_n/tdata_n tneg_n/codes_n tclk_n rclk_n rneg_n/lcv_n rpos_n/rdata_n rlos_n rtip_n rring_n master clock synthesizer qrss pattern generator dmo_n ttip_n tring_n txon_n hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver local analog loopback remote loopback digital loopback hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector network loop detector rx equalizer equalizer control ais detector los detector lbo[3:0] loopback enable ja select nlcd enable qrss enable harware control test reset tratio sr/dr eqc[4:0] tclke rclke rxmute ataos drive monitor dfm mclkout taos_n loop1_n loop0_n
xrt83vl38 3 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator ? receive loss of signal (rlos) output ? on-chip hdb3/b8zs/ami encoder/decoder functions ? qrss pattern generator and detection for testing and monitoring ? error and bipolar violation insertion and detection ? receiver line attenuation indication output in 1db steps ? network loop-code detection for automatic loop-back activation/deactivation ? transmit all ones (taos) and in-band network loop up and down code generators ? supports local analog, remote, digital and dual loop-back modes ? meets or exceeds t1 and e1 short-haul and long-haul network access specificati ons in itu g.703, g.775, g.736 and g.823; tr-tsy-000499; ansi t1.403 and t1.408; etsi 300-166 and at&t pub 62411 ? supports both hardware and host (parallel or serial) microprocessor interface for programming ? programmable interrupt ? low power dissipation ? logic inputs accept either 3.3v or 5v levels ? dual 3.3v and 1.8v supply operation ? 225 ball bga package ? -40c to +85c temperature range ordering information p art n umber p ackage o perating t emperature r ange XRT83VL38IB 225 ball bga -40 c to +85 c
xrt83vl38 4 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 f igure 3. p ackage p in o ut dvdd_dr nc12 rtip_3 rring_3 nc11 rring_2 rtip_2 rneg_2 gauge dvddd_p rtip_6 rring_6 sense ser_ par rring_7 rtip_7 rvdd_7 dgnd 18 rclk_3 rpos_3 tgnd_3 rgnd_3 tvdd_3 ttip_2 rgnd_2 dgnd agnd_bias avdd_bias rpos_6 rgnd_6 rvdd_6 tring_7 rgnd_7 rpos_7 dmo_6 rneg_7 17 rlos_3 rneg_3 ttip_3 rvddd_3 tring_3 tvdd_2 rvdd_2 rclk_2 pts1 rxon int rneg_6 ttip_6 ttip_7 tgnd_7 tgnd_6 rclk_7 tclk_6 16 tclk_2 tneg_3 dmo_2 rpos_2 tgnd_2 tring_2 dgnd rlos_2 rlos_6 dvdd_dr pts2 rclk_6 tvdd_6 tvdd_7 tring_6 rlos_7 tclk_7 tpos_6 15 jasel0 tpos_2 tclk_3 tpos_3 xrt83vl38 (top view) 225 ball bga tneg_7 tpos_7 tneg_6 dmo_7 14 txon_0 jasel1 dmo_3 tneg_2 txon_7 pclk txon_5 txon_4 13 a[7] tx0n_3 txon_2 txon_1 txon_6 rxmute test ict 12 a[3] a[6] a[5] a[4] tersel0 tersel1 rxtsel txtsel 11 a[1] a[2] a[0] dvdd_pdr rxres1 hw_ host dvdd_pdr rxres0 10 dvdd dgnd dgnd dvdd_dr dvdd_dr dgnd d[1] d[3] 9 clksel0 clksel1 clksel2 dgnd dgnd reset d[2] d[4] 8 ale_ as cs rd _ ds wr _r/ w d[0] d[7] d[6] d[5] 7 rdy_ dtack taos_1 taos_3 taos_0 taos_7 taos_4 taos_5 taos_6 6 taos_2 tneg_1 tpos_0 dmo_0 rvdd_1 dmo_4 tclk_5 tpos_5 tneg_5 5 tpos_1 tclk_0 tneg_0 dmo_1 tvdd_0 tvdd_1 ttip_1 rlos_1 dvdd_dr sr_ dr gndpll_2 rneg_5 tring_5 dmo_5 tvdd_4 rneg_4 tneg_4 tpos_4 4 tclk_1 rclk_0 rlos_0 tgnd_0 ttip_0 tring_1 rgnd_1 rclk_1 vddpll_1 gndpll_1 rclk_5 rpos_5 rvdd_5 tgnd_5 tgnd_4 tclk_4 rclk_4 rlos_4 3 rneg_0 rpos_0 rvdd_0 rgnd_0 tring_o tgnd_1 rpos_1 rneg_1 vddpll_2 dgnd rlos_5 rgnd_5 ttip_5 tring_4 ttip_4 rgnd_4 rpos_4 rvdd_4 2 dgnd tdo rtip_0 rring_0 tms rring_1 rtip_1 mclkout mclke1 mclkt1 rtip_5 rring_5 tck tvdd_5 tdi rring_4 rtip_4 dvdd_pdr 1 a b c d e f g h j k l m n p r t u v
xrt83vl38 i rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator general description 1 applications 1 block diagram of the xrt83vl 38 t1/e1/j1 liu (host mode) 1 block diagram of the xrt83vl38 t1/e1/j1 liu (hardware mode) 2 features 2 ordering information 3 package pin out 4 pin description by function 5 receive sections 5 transmitter sections 7 microprocessor interface 11 jitter attenuator 14 clock synthesizer 14 alarm functions/redundancy support 16 serial microprocessor interface 20 power and ground 21 functional description 23 master clock generator 23 two input clock source 23 one input clock source 23 master clock generator 24 24 receiver 24 receiver input 24 receive monitor mode 25 receiver loss of signal (rlos) 25 simplified diagram of -15db t1/e1 s hort haul mode and rlos condition 25 simplified diagram of -29db t1/e 1 gain mode and rlos condition 26 simplified diagram of -36db t1/e1 long haul mode and rlos condition 26 simplified diagram of extended rlos mode (e1 only) 27 receive hdb3/b8zs decoder 27 recovered clock (rclk) sampling edge 27 receive clock and output data timing 28 jitter attenuator 28 gapped clock (ja must be enabled in the transmit path) 28 maximum gap width for multip lexer/mapper applications 28 arbitrary pulse generator for t1 and e1 29 arbitrary pulse segment assignment 29 transmitter 29 digital data format 29 transmit clock (tclk) sampling edge 29 transmit clock and input data timing 30 transmit hdb3/b8zs encoder 30 examples of hdb3 encoding 30 examples of b8zs encoding 30 30 driver failure monitor (dmo) 31
xrt83vl38 ii octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 transmit pulse shaper & line build out (lbo) circuit 31 receive equalizer contro l and transmit line build-out settings 31 transmit and receive terminations 33 receiver (channels 0 - 7) 33 internal receive termination mode 33 receive termination control 33 simplified diagram for the internal re ceive and transmit termination mode 33 receive terminations 34 simplified diagram for t1 in the external termination mode (rxts el= 0 & txtsel= 0) 34 simplified diagram for e1 in external receive te rmination mode (rxtsel= 0) and internal trans- mit termination mode (txtel= 1) 35 transmitter (channels 0 - 7) 35 transmit termination mode 35 termination select control 35 external transmit termination mode 35 transmit terminations 36 36 36 redundancy applications 36 typical redundancy schemes 37 simplified block diagram of the tran smit section for 1:1 & 1+1 redundancy 38 simplified block diagram - receive section for 1:1 and 1+1 redundancy 38 simplified block diagram - tran smit section for n+1 redundancy 39 simplified block diagram - rece ive section for n+1 redundancy 40 pattern transmit and detect function 41 pattern transmission control 41 transmit all ones (taos) 41 network loop code detection and transmission 41 loop-code detec tion control 41 transmit and detect quasi-random signal source (tdqrss) 42 loop-back modes 43 loop-back control in hardware mode 43 loop-back control in host mode 43 local analog loop-back (aloop) 43 local analog loop-back signal flow 43 remote loop-back (rloop) 44 remote loop-back mode with jitter a ttenuator selected in receive path 44 remote loop-back mode with jitter a ttenuator selected in transmit path 44 digital loop-back (dloop) 45 digital loop-back mode with jitter at tenuator selected in transmit path 45 dual loop-back 45 signal flow in dual loop-back mode 45 microprocessor interface 46 serial microprocessor interface block 46 simplified block diagram of the serial microprocessor interface 46 serial timing information 46 timing diagram for the serial microprocessor interface 46
xrt83vl38 iii rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 24-bit serial data input descritption 46 addr[7:0] (sclk1 - sclk8) 47 r/w (sclk9) 47 dummy bits (sclk10 - sclk16) 47 data[7:0] (sclk17 - sclk24) 47 8-bit serial data ou tput description 47 timing diagram for the micropr ocessor serial interface 47 microprocessor serial interface timings ( ta = 250c, vdd=3.3v 5% and load = 10pf) 48 48 parallel microprocesso r interface block 48 selecting the micropro cessor interface mode 48 simplified block diag ram of the microproce ssor interface block 49 the microprocessor interface block signals 49 xrt83vl38 microprocessor interface si gnals that exhibit constant roles in both intel and motorola modes 49 intel mode: microprocessor interface signals 50 motorola mode: mi croprocessor interface signals 50 intel mode programmed i/o access (asynchronous) 50 intel p interface signals during programme d i/o read and write operations 51 motorola mode programmed i/o access (asynchronous) 52 intel microprocessor interface timing specifications 52 motorola 68k p interface signa ls during programmed i/o re ad and write operations 53 motorola 68k microp rocessor interface timing specifications 53 microprocessor regi ster tables 53 microprocessor register address 54 microprocessor register bit description 54 microprocessor register descriptions 57 microprocessor register #0, bit description 57 microprocessor register #1, bit description 59 microprocessor register #2, bit description 61 microprocessor register #3, bit description 63 microprocessor register #4, bit description 64 microprocessor register #5, bit description 66 microprocessor register #6, bit description 68 microprocessor register #7, bit description 69 microprocessor register #8, bit description 70 microprocessor register #9, bit description 70 microprocessor register #10, bit description 71 microprocessor register #11, bit description 71 microprocessor register #12, bit description 72 microprocessor register #13, bit description 72 microprocessor register #14, bit description 73 microprocessor register #15, bit description 73 microprocessor register #128, bit description 74 clock select register 75 register 0x81h sub registers 75 microprocessor register #129, bit description 75
xrt83vl38 iv octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 microprocessor register #130, bit description 76 microprocessor register #131, bit description 77 microprocessor register #192, bit description 78 electrical characteristics 79 absolute maximum ratings 79 dc digital input and output electrical characteristics 79 xrt83vl38 power consumption 79 e1 receiver electri cal characteristics 80 t1 receiver electri cal characteristics 81 e1 transmit return loss requirement 81 e1 transmitter electrical characteristics 82 t1 transmitter electrical characteristics 82 itu g.703 pulse template 83 transmit pulse mask specification 83 itu g.703 section 13 synchronous interface pulse template 84 e1 synchronous interface transmit pulse mask specification 84 dsx-1 pulse template (normalized amplitude) 85 dsx1 interface isolated pulse mask and corner points 85 ac electrical characteristics 86 transmit clock and input data timing 86 receive clock and output data timing 87 microprocessor interface i/o timing 87 intel interface timing - asynchronous 87 intel asynchronous programmed i/o interface timing 87 asynchronous mode 1 - intel 8051 and 80188 interface timing 88 motorola asychronous interface timing 89 motorola 68k asynchronous progr ammed i/o interface timing 89 asynchronous - motorola 68k - interface timing specification 89 microprocessor interface timi ng - reset pulse width 89 package dimensions 90 225 ball plastic ball grid array (bottom view) 90 (19.0 x 19.0 x 1.0mm) 90 ordering information 91 revisions 91
xrt83vl38 5 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator pin description by function receive sections s ignal n ame l ead # t ype d escription rxon k16 i receiver on - harware mode writing a ?1? to this pin in hardware mode turns on the receive sections of all chan - nels. writing a ?0? shuts off the re ceiver sections of all channels. rlos_0 rlos_1 rlos_2 rlos_3 rlos_4 rlos_5 rlos_6 rlos_7 c3 h4 h15 a16 v3 l2 j15 t15 o receiver loss of signal for channel_ 0: this output signal go es ?high? for at least one rclk_0 cycle to indicate loss of signal at the receive 0 input. rlos will remain ?high? for the entire duration of the loss of sig - nal detected by the receiver logic. see?receiver loss of signal (rlos)? on page 25. receiver loss of signal for channel _1 receiver loss of signal for channel _2 receiver loss of signal for channel _3 receiver loss of signal for channel _4 receiver loss of signal for channel_ 5 receiver loss of signal for channel _6 receiver loss of signal for channel _7 rclk_0 rclk_1 rclk_2 rclk_3 rclk_4 rclk_5 rclk_6 rclk_7 b3 h3 h16 a17 u3 l3 m15 u16 o receiver clock output for channel _0 receiver clock output for channel _1 receiver clock output for channel _2 receiver clock output for channel _3 receiver clock output for channel _4 receiver clock output for channel _5 receiver clock output for channel _6 receiver clock output for channel _7 rneg_0 lcv_0 rneg_1 lcv_1 rneg_2 lcv_2 rneg_3 lcv_3 rneg_4 lcv_4 rneg_5 lcv_5 rneg_6 lcv_6 rneg_7 lcv_7 a2 a2 h2 h18 b16 t4 m4 m16 v17 o receiver negative data output for channel_0 - dual-rail mode this signal is the receive negative-rail output data. line code violation output for channel_0 - single-rail mode this signal goes ?high? for one rclk_0 cycle to indicate a code violation is detected in the received data of channel _0. if ami c oding is selected, every bipolar violation received will cause this pin to go ?high?. receiver negative data output for channel _1 line code violation output for channel _1 receiver negative data output for channel _2 line code violation output for channel _2 receiver negative data output for channel _3 line code violation output for channel _3 receiver negative data output for channel _4 line code violation output for channel _4 receiver negative data output for channel _5 line code violation output for channel _5 receiver negative data output for channel _6 line code violation output for channel _6 receiver negative data output for channel _7 line code violation output for channel _7
xrt83vl38 6 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 rpos_0 rdata_0 rpos_1 rdata_1 rpos_2 rdata_2 rpos_3 rdata_3 rpos_4 rdata_4 rpos_5 rdata_5 rpos_6 rdata_6 rpos_7 rdata_7 b2 b2 g2 d15 b17 u2 m3 l17 t17 o receiver positive data output for channel _0 - dual-rail mode this signal is the receive positive-rail output data sent to the framer. receiver nrz data output fo r channel _0 - single-rail mode this signal is the receive output data. receiver positive data output for channel _1 receiver nrz data output for channel _1 receiver positive data output for channel _2 receiver nrz data output for channel _2 receiver positive data output for channel _3 receiver nrz data output for channel _3 receiver positive data output for channel _4 receiver nrz data output for channel _4 receiver positive data output for channel _5 receiver nrz data output for channel _5 receiver positive data output for channel _6 receiver nrz data output for channel 6 receiver positive data output for channel _7 receiver nrz data output for channel _7 rtip_0 rtip_1 rtip_2 rtip_3 rtip_4 rtip_5 rtip_6 rtip_7 c1 g1 g18 c18 u1 l1 l18 t18 i receiver differential tip input for channel _0 positive differential receive input from the line receiver differential tip input for channel _1 receiver differential tip input for channel _2 receiver differential tip input for channel _3 receiver differential tip input for channel _4 receiver differential tip input for channel _5 receiver differential tip input for channel _6 receiver differential tip input for channel _7 rring_0 rring_1 rring_2 rring_3 rring_4 rring_5 rring_6 rring_7 d1 f1 f18 d18 t1 m1 m18 r18 i receiver differential ring input for channel _0 negative differential receive input from the line receiver differential ring input for channel _1 receiver differential ring input for channel _2 receiver differential ring input for channel _3 receiver differential ring input for channel _4 receiver differential ring input for channel _5 receiver differential ring input for channel _6 receiver differential ring input for channel _7 rxmute t12 i receive data muting when a los condition occurs, the outputs rpos_n/rneg_n will be muted, (forced to ground) to prevent data chattering. tie this pin ?low? to disable the muting function. n otes : 1. this pin is internally pulled ?high? with a 50k ? resistor. 2. in hardware mode , all receive channels share the same rxmute control function. s ignal n ame l ead #t ype d escription
xrt83vl38 7 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator transmitter sections rxres1 rxres0 r10 v10 i receive external resistor control pins - hardware mode receive external resistor control pin 1: receive external resistor control pin 0: these pins determine the value of the external receive fixed resistor according to the following table: n ote : these pins are internally pulled ?low? with a 50k ? resistor. rclke pts1 j16 j16 i receive clock edge - hardware mode set this pin ?high? to sample rpos_n/rneg_n on the falling edge of rclk_n. with this pin tied ?low?, output data are updated on the rising edge of rclk_n. microprocessor type select input pin 1 - host mode this pin along with pts2 (pin 128) is used to select the microprocessor type. see?microprocessor type select in put pins - host mode:? on page 12. n ote : this pin is internally pulled ?low? with a 50k ? resistor. s ignal n ame l ead # t ype d escription e pts2 l15 l15 i transmit clock edge - hardware mode set this pin ?high? to sample transmit input data on the rising edge of tclk_n. with this pin tied ?low?, input data are sampled on the falling edge of tclk_n. microprocessor type select input pin 2 - host mode this pin along with pts1 (pin 133) selects the microprocessor type. see?micro - processor type select input pins - host mode:? on page 12. n ote : this pin is internally pulled ?low? with a 50k ? resistor. ttip_0 ttip_1 ttip_2 ttip_3 ttip_4 ttip_5 ttip_6 ttip_7 e3 g4 f17 c16 r2 n2 n16 p16 o transmitter tip output for channel _0 positive differential transmit output to the line. transmitter tip output for channel _1 transmitter tip output for channel _2 transmitter tip output for channel _3 transmitter tip output for channel _4 transmitter tip output for channel _5 transmitter tip output for channel _6 transmitter tip output for channel _7 s ignal n ame l ead #t ype d escription rxres1 0 0 required fixed external rx resistor no external fixed resistor 240 ? rxres0 0 1 1 1 210 ? 150 ? 0 1
xrt83vl38 8 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 tring_0 tring_1 tring_2 tring_3 tring_4 tring_5 tring_6 tring_7 e2 f3 f15 e16 p2 n4 r15 p17 o transmitter ring ou tput for channel _0 negative differential transmit output to the line. transmitter ring ou tput for channel _1 transmitter ring ou tput for channel _2 transmitter ring ou tput for channel _3 transmitter ring ou tput for channel _4 transmitter ring ou tput for channel _5 transmitter ring ou tput for channel _6 transmitter ring ou tput for channel _7 tpos_0 tdata_0 tpos_1 tdata_1 tpos_2 tdata_2 tpos_3 tdata_3 tpos_4 tdata_4 tpos_5 tdata_5 tpos_6 tdata_6 tpos_7 tdata_7 c5 a4 b14 d14 v4 u5 v15 t14 i transmitter positive data input for channel _0 - dual-rail mode this signal is the positive-rail input data for transmitter 0. transmitter 0 data in put - single-rail mode this pin is used as the nrz input data for transmitter 0. transmitter positive data input for channel _1 transmitter 1 data input transmitter positive data input for channel _2 transmitter 2 data input transmitter positive data input for channel _3 transmitter 3 data input transmitter positive data input for channel _4 transmitter 4 data input transmitter positive data input for channel _5 transmitter 5 data input transmitter positive data input for channel _6 transmitter 6 data input transmitter positive data input for channel _7 transmitter 7 data input n ote : internally pulled ?low? with a 50k ? resistor for each channel. s ignal n ame l ead #t ype d escription
xrt83vl38 9 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator tneg_0 codes_0 tneg_1 codes_1 tneg_2 codes_2 tneg_3 codes_3 tneg_4 codes_4 tneg_5 codes_5 tneg_6 codes_6 tneg_7 codes_7 c4 c4 b5 d13 b15 u4 v5 u14 r14 i transmitter negative nrz da ta input for channel _0 dual-rail mode this signal is the negative-rail input data for transmitter 0. single-rail mode this pin can be left unconnected. coding select for channel _0 - ha rdware mode and single-rail mode connecting this pin ?low? enables hdb3 in e1 or b8zs in t1 encoding and decoding for channel _0. connecting this pin ?high? selects ami data format. transmitter negative nrz da ta input for channel _1 coding select for channel _1 transmitter negative nrz da ta input for channel _2 coding select for channel _2 transmitter negative nrz da ta input for channel _3 coding select for channel _3 transmitter negative nrz da ta input for channel _4 coding select for channel _4 transmitter negative nrz da ta input for channel _5 coding select for channel _5 transmitter negative nrz da ta input for channel _6 coding select for channel _6 transmitter negative nrz da ta input for channel _7 coding select for channel _7 n ote : internally pulled ?low? with a 50k ? resistor for each channel. tclk_0 tclk_1 tclk_2 tclk_3 tclk_4 tclk_5 tclk_6 tclk_7 b4 a3 a15 c14 t3 t5 v16 u15 i transmitter clock input for channel _0 - host mode and hardware mode e1 rate at 2.048mhz 50ppm. t1 rate at 1.544mhz 32ppm. during normal operation tclk_0 is used for sampling input data at tpos_0/ tdata_0 and tneg_0/codes_0 while mclk is used as the timing reference for the transmit pulse shaping circuit. transmitter clock input for channel _1 transmitter clock input for channel _2 transmitter clock input for channel _3 transmitter clock input for channel _4 transmitter clock input for channel _5 transmitter clock input for channel _6 transmitter clock input for channel _7 n ote : internally pulled ?low? with a 50k ? resistor for all channels. s ignal n ame l ead #t ype d escription
xrt83vl38 10 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 taos_0 taos_1 taos_2 taos_3 taos_4 taos_5 taos_6 taos_7 d6 b6 a5 c6 t6 u6 v6 r6 i transmit all ones for channel _0 - hardware mode setting this pin ?high? enables the transmission of an ?all ones? pattern from channel _0. a ?low? level stops the transmission of the ?all ones? pattern. transmit all ones for channel _1 transmit all ones for channel _2 transmit all ones for channel _3 transmit all ones for channel _4 transmit all ones for channel _5 transmit all ones for channel _6 transmit all ones for channel _7 n ote : internally pulled ?low? with a 50k ? resistor for all channels. txon_0 txon_1 txon_2 txon_3 txon_4 txon_5 txon_6 txon_7 a13 d12 c12 b12 v13 u13 r12 r13 i transmitter turn on for channel _0 hardware mode setting this pin "high" turns on the transmit and receive sections of channel _0. when txon_0 = ?0? then ttip_0 and tring_0 driver outputs will be tri-stated. in host mode the txon_n bits in the channel control r egisters turn each channel transmit and receive section on or off. however, control of the on/off function can be transferred to the hardware pins by setting the txoncntl bit (b it 7) to ?1? in the register at address hex 0x82. transmitter turn on for channel _1 transmitter turn on for channel _2 transmitter turn on for channel _3 transmitter turn on for channel _4 transmitter turn on for channel _5 transmitter turn on for channel _6 transmitter turn on for channel _7 n ote : internally pulled ?low? with a 50k ? resistor for all channels. s ignal n ame l ead #t ype d escription
xrt83vl38 11 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator microprocessor interface s ignal n ame l ead # t ype d escription hw_ host t10 i mode control input this pin selects hardware or host mode . leave this pin unconnected or tie ?high? to select hardware mode . for host mode , this pin must be tied ?low?. n ote : internally pulled ?high? with a 50k ? resistor. wr _r/ w eqc0 d7 d7 i write input (read/write) - host mode: intel bus timing : a ?low? pulse on wr selects a write operation when cs pin is ?low?. motorola bus timing: a ?high? pulse on r/ w selects a read operation and a ?low? pulse on r/ w selects a write operation when cs is ?low?. equalizer control input pin 0 - hardware mode pins eqc0, eqc1, eqc2, eqc3 and eqc4 select the receive equalizer and transmitter line build out. see?receive equali zer control and transmit line build-out settings? on page 31. n ote : internally pulled ?low? with a 50k ? resistor. rd _ ds eqc1 c7 c7 i read input (data strobe) - host mode intel bus timing: a ?low? pulse on rd selects a read operation when the cs pin is ?low?. motorola bus timing: a ?low? pulse on ds indicates a read or write operation when the cs pin is ?low?. equalizer control input pin 1 - hardware mode pins eqc0, eqc1, eqc2, eqc3 and eqc4 select the receive equalizer and transmitter line build out. see?receive equali zer control and transmit line build-out settings? on page 31. n ote : internally pulled ?low? with a 50k ? resistor. ale_ as eqc2 a7 a7 i address latch input (address strobe) - host mode intel bus timing: the address inputs are latched into the internal register on the fall - ing edge of ale. motorola bus timing: the address inputs are latched into the internal register on the falling edge of as . equalizer control input pin 2 - hardware mode pins eqc0, eqc1, eqc2, eqc3 and eqc4 select the receive equalizer and transmitter line build out. see?receive equali zer control and transmit line build-out settings? on page 31. n ote : internally pulled ?low? with a 50k ? resistor. cs eqc3 b7 b7 i chip select input - host mode: this signal must be ?low? in order to access the parallel port. equalizer control input pin 3 - hardware mode: pins eqc0, eqc1, eqc2, eqc3 and eqc4 select the receive equalizer and transmitter line build out. see?receive equali zer control and transmit line build-out settings? on page 31. n ote : internally pulled ?low? with a 50k ? resistor.
xrt83vl38 12 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 rdy_ dtack eqc4 a6 a6 o i ready output (data transfer acknowledge output) - host mode intel bus timing : rdy is asserted ?high? to indicate the device has completed a read or write operation. motorola bus timing : dtack is asserted ?low? to indicate the device has com - pleted a read or write cycle. equalizer control input pin 4 - hardware mode pins eqc0, eqc1, eqc2, eqc3 and eqc4 select the receive equalizer and transmitter line build out. see?receive equali zer control and transmit line build-out settings? on page 31. n ote : internally pulled ?low? with a 50k ? resistor. pts1 pts2 rclke tclke j16 l15 j16 l15 i microprocessor type select input pins - host mode: microprocessor type select input bit 1 microprocessor type select input bit 2 receive clock edge - hardware mode see?receive clock edge - hardware mode? on page 7. transmit clock edge - hardware mode see?transmit clock edge - hardware mode? on page 7. n ote : these pins are internally pulled ?low? with a 50k ? resistor. d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]/sdo loop1_4 loop0_4 loop1_5 loop0_5 loop1_6 loop0_6 loop1_7 loop0_7 t7 u7 v7 v8 v9 u8 u9 r7 t7 u7 v7 v8 v9 u8 u9 r7 i/o microprocessor read/write data bus pins - host mode data bus[7] data bus[6] data bus[5] data bus[4] data bus[3] data bus[2] data bus[1] data bus[0] if ser_ par = 0 or serial data input if ser_ par = 1 loop-back control pins, bits [1:0 ] channel_[7:4] - hardware mode pins 67-74 and 173-180 control which loop -back mode is selected per channel. see?loop-back control pins, bi ts [1:0] channel_[7:0]? on page 17. n ote : internally pulled ?low? with a 50k ? resistor for all channels. s ignal n ame l ead #t ype d escription ? pts2 ? pts1 0 0 0 1 1 0 ? p type intel 8051 asynchronous motorola asynchronous power pc synchronous mpc8xx motorola synchronous 1 1
xrt83vl38 13 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0]/sdi loop1_3 loop0_3 loop1_2 loop0_2 loop1_1 loop0_1 loop1_0 loop0_0 a12 b11 c11 d11 a11 b10 a10 c10 a12 b11 c11 d11 a11 b10 a10 c10 i microprocessor interface address bus pins - host mode: microprocessor interface address bus[7] microprocessor interface address bus[6] microprocessor interface address bus[5] microprocessor interface address bus[4] microprocessor interface address bus[3] microprocessor interface address bus[2] microprocessor interface address bus[1] microprocessor interface address bus[0] if ser_ par = 0 or serial data input if ser_ par = 1 loop-back control pins, bits [1:0] channel_[3:0] in hardware mode , pins 67-74 and 173-180 control which loop-back mode is selected per channel. see?loop-back control pins, bits [1:0] channel_[7:0]? on page 17. n ote : these pins are internally pulled ?low? with a 50k ? resistor. pclk/sclk ataos t13 t13 i microprocessor clock input - host mode: pclk - input clock for synchronous parrallel microprocessor operation. maximum clock rate is 54 mhz, ser_ par = 0 sclk - input serial clock fo r spi interface, ser_ par = 1 n ote : this pin is internally pulled ?low? with a 50k ? resistor for asynchronous microprocessor interface when no clock is present. automatic transmit ?all ones? - hardware mode this pin functions as an automatic transmit ?all ones?. see?automatic transmit ?all ones? pattern - hardware mode? on page 16. int tratio l16 l16 o i interrupt output - host mode this pin goes ?low? to indicate an alarm condition has occurred within the device. interrupt generation can be globally disabled by setting the gie bit to a ?0? in the command control register. transmitter transformer ratio select - hardware mode tratio is not supported in the 83vl38. this pin is for int only. n ote : this pin is an open drain output and requires an external 10k ? pull-up resistor. s ignal n ame l ead #t ype d escription
xrt83vl38 14 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 jitter attenuator clock synthesizer s ignal n ame l ead # t ype d escription jasel0 jasel1 a14 b13 i jitter attenuator select pins hardware mode jitter attenuator select bit 0 jitter attenuator select bit 1 jasel[1:0] pins are used to place the jitter at tenuator in the transmit path, the receive path or to disable it. n ote : these pins are internally pulled ?low? with 50k ? resistors. s ignal n ame l ead # t ype d escription mclkout h1 o synthesized master clock output this signal is the output of the master clock synthesizer pll which is at t1 or e1 rate based upon the mode of operation. mclkt1 k1 i t1 master clock input this signal is an independent 1.544mhz clo ck for t1 systems with accuracy better than 50ppm and duty cycle within 40% to 60%. mclkt1 is used in the t1 mode. n otes : 1. all channels of the xrt83vl38 must be operated at the same clock rate, either t1, e1 or j1. 2. see pin 26 description for further explanation for the usage of this pin. 3. internally pulled ?low? with a 50k ? resistor. mclke1 j1 i e1 master clock input a 2.048mhz clock for with an accuracy of be tter than 50ppm and a duty cycle of 40% to 60% can be provided at this pin. in systems that have only one master clock source availabl e (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. n otes : 1. all channels of the xrt83vl38 must be operated at the same clock rate, either t1, e1 or j1. 2. internally pulled ?low? with a 50k ? resistor. jasel1 jasel0 0 1 1 0 1 1 0 0 disabled rx & tx paths receive path transmit path ja path
xrt83vl38 15 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator clksel0 clksel1 clksel2 a8 b8 c8 i clock select inputs for master clock synthesizer - hardware mode clksel[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an external accurate clock source according to the table below. in hardware mode, the mclkrate control signal is generated from the state of eqc[4:0] inputs. in host mode, the state of these pins are ignored and the master frequency pll is con - trolled by the corresponding interface bits. see table 40 register address 10000001 n ote : these pins are internally pulled ?low? with a 50k ? resistor. s ignal n ame l ead #t ype d escription 2048 2048 2048 1544 mclke1 khz 2048 2048 1544 1544 mclkt1 khz 1544 1544 2048 1544 2048 clkout khz 1544 2048 1544 0 0 1 1 clksel0 0 0 0 0 clksel1 0 0 0 0 clksel 2 0 1 0 0 0 0 1544 2048 0 1 0 1 mclkrate 1 0
xrt83vl38 16 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 alarm functions/redundancy support s ignal n ame l ead # t ype d escription gauge j18 i twisted pair cable wire gauge select - hardware mode connect this pin ?high? to select 26 gauge wire. connect this pin ?low? to select 22 and 24 gauge wire for all channels. n ote : internally pulled ?low? with a 50k ? resistor. dmo_0 dmo_1 dmo_2 dmo_3 dmo_4 dmo_5 dmo_6 dmo_7 d5 d4 c15 c13 r5 p4 u17 v14 o driver failure monitor channel _0: this pin transitions ?high? if a short circuit condition is detected in the transmit driver of channel _0, or no transmit output pulse is detected for more than 128 tclk_0 cycles. driver failure monitor channel _1 driver failure monitor channel _2 driver failure monitor channel _3 driver failure monitor channel _4 driver failure monitor channel _5 driver failure monitor channel _6 driver failure monitor channel _7 ataos pclk/sclk t13 t13 i automatic transmit ?all ones ? pattern - hardware mode a "high" level on this pin enables the auto matic transmission of an "all ones" ami pat - tern from the transmitter of any channel that the receiver of that channel has detected an los condition. a "low" level on this pin disables this function. note: all channels share the same ataos control function. microprocessor clock input - host mode see?microprocessor clock input - host mode:? on page 13. n ote : this pin is internally pulled ?low? fo r asynchronous microprocessor interface when no clock is present. tratio int l16 l16 i o transmitter transformer rati o select - hardware mode tratio is not supported in the 83vl38. this pin is for int only.. interrupt output - host mode this pin is asserted ?low? to indicate an alarm condition. see?interrupt out - put - host mode? on page 13. n ote : this pin is an open drain output and requires an external 10k ? pull-up resistor. reset t8 i hardware reset (active ?low?): when this pin is tied ?low? for more than 10s, the device is put in the reset state. exar recommends initiating a harware reset upon power up. n ote : this pin is internally pulled ?high? with a 50k ? resistor. sr/ dr k4 i single-rail/dual-rail data format: connect this pin ?low? to select transmit and receive data format in dual-rail mode . in this mode, hdb3 or b8zs enc oder and decoder are not available. connect this pin ?high? to select single-rail data format . n ote : internally pulled ?low? with a 50k ? resistor.
xrt83vl38 17 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator loop1_0 loop0_0 loop1_1 loop0_1 loop1_2 loop0_2 loop1_3 loop0_3 loop1_4 loop0_4 loop1_5 loop0_5 loop1_6 loop0_6 loop1_7 loop0_7 a[1] a[0]/sdi a[3] a[2] a[5] a[4] a[7] a[6] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]/sdo a10 c10 a11 b10 c11 d11 a12 b11 t7 u7 v7 v8 v9 u8 u9 r7 a10 c10 a11 b10 c11 d11 a12 b11 t7 u7 v7 v8 v9 u8 u9 r7 i loop-back control pins, bi ts [1:0] channel_[7:0] loop-back control bit 1, channel _0 loop-back control bit 0, channel _0 loop-back control bit 1, channel _1 loop-back control bit 0, channel _1 loop-back control bit 1, channel _2 loop-back control bit 0, channel _2 loop-back control bit 1, channel _3 loop-back control bit 0, channel _3 loop-back control bit 1, channel _4 loop-back control bit 0, channel _4 loop-back control bit 1, channel _5 loop-back control bit 0, channel _5 loop-back control bit 1, channel _6 loop-back control bit 0, channel _6 loop-back control bit 1, channel _7 loop-back control bit 0, channel _7 in hardware mode , these pins control the loop-back mode for each channel_n per the following table. microprocessor address a[7:0] and data bus pins d[7:0] - host mode these pins are microprocessor address and data bus pins. see?microproces - sor interface address bus pins - host mode:? on page 13. and see ?microprocessor read/write data bus pins - host mode? on page 12. n ote : these pins are internally pulled ?low? with a 50k ?? resistor. s ignal n ame l ead #t ype d escription loop1_n loop0_n 0 0 0 1 1 0 1 1 mode normal mode no loop-back channel_n local loop-back channel_n remote loop-back channel_n digital loop-back channel_n
xrt83vl38 18 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 eqc4 eqc3 eqc2 eqc1 eqc0 rdy _ dtack cs ale_ as rd _ ds wr _r/ w a6 b7 a7 c7 d7 a6 b7 a7 c7 d7 i i i i i o i i i i equalizer control input 4 - hardware mode this pin together with pins eqc[3:0] is used to control the transmit pulse shaping, transmit line build-out (lbo) and receive monitoring while operating at one of either the t1, e1 or j1 clock rates/modes. see?receive equa lizer control and transmit line build-out settings? on page 31. for description of transmit equalizer control bits. equalizer control input 3 equalizer control input 2 equalizer control input 1 equalizer control input 0 n otes : 1. in hardware mode all transmit channels share the same pulse setting controls function. 2. all channels of an xrt83vl38 must operate at the same clock rate, either the t1, e1 or j1 modes. in host mode , these pins perform various microprocessor functions. see?micro - processor interface? on page 11. n ote : internally pulled ?low? with a 50k ? resistor. rxtsel u11 i receiver termination select in hardware mode , when this pin is ?low? the receive line termination is determined only by an external resistor. when ?high? , the receive termination is realized by the internal resistor or the combination of intern al and external resistors. these conditions are described in the table below. n ote : in hardware mode all channels share the same rxtsel control function. in host mode , the rxtsel_n bits in the channel control registers determine if the receiver termination is external or inter nal. however, the function of rxtsel can be transferred to the hardware pin by setting the tercntl bit (bit 6) to ?1? in the register address hex 0x82. n ote : this pin is internally pulled ?low? with a 50k ? resistor. txtsel v11 i transmit termination se lect - hardware mode when this pin is ?low? the transmit line termination is determined only by an external resistor. when ?high?, the transmit termination is realized only by the internal resistor. n otes : 1. this part does not support external termination in e1 operation. 2. this pin is internally pulled ?low? with a 50k ? resistor. 3. in hardware mode all channels share the same txtsel control function. s ignal n ame l ead #t ype d escription rxtsel rx termination 0 1 external internal txtsel tx termination 0 1 external internal
xrt83vl38 19 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator tersel1 tersel0 t11 r11 i termination impedance select bit 1: termination impedance select bit 0: in the hardware mode and in the internal termination mode (txtsel=?1? and rxt - sel=?1?) tersel[1:0] control the transmit and receive termination impedance according to the following table. in the internal termination mode the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor (see descripti on of rxres[1:0] pins). in the internal termination mode the transformer ratio of 1:2 and 1:1 is required for transmitter and receiver respectively with the transmitter output ac coupled to the transformer. n otes : 1. this pin is internally pulled ?low? with a 50k ? resistor. 2. in hardware mode , all channels share the same tersel control function. 3. in the external termination mode a 1:2 transformer ratio must be used for the transmitter. test u12 i manufacturing test: n ote : for normal operation this pin must be tied to ground. ict v12 i in-circuit testing (active ?low?): when this pin is tied ?low?, all output pins are forced to a high impedance state for in- circuit testing. pulling reset and ict pins ?low? simultaneously will put the chip in factory test mode. this condition should not be permitted during normal operation. n ote : this pin is internally pulled ?high? with a 50k ? resistor. s ignal n ame l ead #t ype d escription 0 1 1 0 1 1 0 0 100 ? 110 ? 75 ? 120 ? termination tersel1 tersel0
xrt83vl38 20 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 serial microprocessor interface s ignal n ame bga l ead # t ype d escription ser_ par p18 i serial/parallel select input (host mode only) this pin is used in the host mode to select between the parallel microprocessor or serial interface. by default, the host mode operates in the parallel micropro - cessor mode. to configure the device for a serial interface, this pin must be pulled "high". n ote : internally pulled ?low? with a 50k ? resistor. sclk t13 i serial clock input (host mode only) if pin ser_ par is pulled "high", this input pin is used the timing reference for the serial microprocessor interface. see the microprocessor section of this datasheet for details. sdi c10 i serial data input (host mode only) if pin ser_ par is pulled "high", this input pin from the serial interface is used to input the serial data for read and write operations. see the microprocessor section of this datasheet for details. sdo r7 o serial data output (host mode only) if pin ser_ par is pulled "high", this output pin from the serial interface is used to read back the regsiter contents. see the microprocessor section of this datasheet for details. tdo b1 test data out this pin is used as the output data pin for the boundary scan chain. tdi r1 test data in this pin is used as the input data pin for the boundary scan chain. for normal operation, this pin should be pulled "high". n ote : internally pulled ?high? with a 50k ? resistor. tck n1 test clock input this pin is used as the input clock source for the boundary scan chain. for normal operation, this pin should be pulled "high". n ote : internally pulled ?high? with a 50k ? resistor. tms e1 test mode select this pin is used as the input mode select for the boundary scan chain. for normal operation, this pin should be pulled "high". n ote : internally pulled ?high? with a 50k ? resistor. sense n18 o factory test pin this pin shpould be left floating.
xrt83vl38 21 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator power and ground s ignal n ame l ead # t ype d escription tgnd_0 tgnd_1 tgnd_2 tgnd_3 tgnd_4 tgnd_5 tgnd_6 tgnd_7 d3 f2 e15 c17 r3 p3 t16 r16 **** transmitter analog ground for channel _0 it is recomended that all ground pins form this device be tied together . tvdd_0 tvdd_1 tvdd_2 tvdd_3 tvdd_4 tvdd_5 tvdd_6 tvdd_7 e4 f4 f16 e17 r4 p1 n15 p15 **** transmitter analog power supply (3.3v + 5%) tvdd can be shared with dvdd. however, it is recommended that tvdd be iso - lated from the analog supply rvdd. for best results use an internal power plane for isolation. if an internal power plane is not available, a ferite bead can be used. each power supply pin should be bypassed to ground with an external 0.1uf capci - tor. rvdd_0 rvdd_1 rvdd_2 rvdd_3 rvdd_4 rvdd_5 rvdd_6 rvdd_7 c2 e5 g16 d16 v2 n3 n17 u18 **** receiver analog positive supply (3.3v 5%) rvdd should not be shared with any other supply. it is recommended that rvdd be isolated from the digital supply dv dd and the analog power supply tvdd. for best results use an internal power plane for isolation. if an internal power plane is not available, a ferite bead can be used. each power supply pin should be bypassed to ground with an external 0.1uf capcitor. rgnd_0 rgnd_1 rgnd_2 rgnd_3 rgnd_4 rgnd_5 rgnd_6 rgnd_7 d2 g3 g17 d17 t2 m2 m17 r17 **** receiver analog ground for channel_0 it is recomended that all ground pins form this device be tied together . avdd k17 j3 j2 **** analog positive supply (1.8v 5%) avdd should be isolated from other supplies. for best results use an internal power plane for isolation. if an internal power plane is not available, a ferite bead can be used. each power supply pin s hould be bypassed to ground with at least one 0.1uf capcitor agnd j17 k3 l4 **** analog ground it is recomended that all ground pins form this device be tied together . dvdd1v8 u10 k18 d10 a9 v1 digital positive supply (1.8v 5%) dvdd1v8 should be isolated from other analog supplies. for best results use an internal power plane for isolation. if an internal power plane is not available, a fer - ite bead can be used. every two dvdd1v8 power supply pins should be bypassed to ground with at least one 0.1uf capcitor
xrt83vl38 22 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 dvdd3v3 r9 k15 j4 d9 a18 **** digital positive supply (3.3v 5%) dvdd3v3 should be isolated from other analog supplies. for best results use an internal power plane for isolation. if an internal power plane is not available, a fer - ite bead can be used. every two dvdd3v3 power supply pins should be bypassed to ground with at least one 0.1uf capcitor dgnd a1 r8 t9 h17 b9 d8 c9 g15 k2 v18 **** digital ground it is recomended that all ground pins form this device be tied together . nc11 nc12 e18 b18 no connect pin s ignal n ame l ead #t ype d escription
xrt83vl38 23 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator functional description the xrt83vl38 is a fully integrated long-haul and short-h aul transceiver intended for t1, j1 or e1 systems. simplified block diagrams of the chip are shown in figure 1 , host mode and figure 2 , hardware mode. the xrt83vl38 can receive signals that have been attenuat ed from 0 to 36db at 772khz (0 to 6000 feet cable loss) for t1 and from 0 to 43 db at 1024khz for e1 systems. in t1 applications, the xrt83vl38 can generate five tr ansmit pulse shapes to meet the short-haul digital cross-connect (dsx-1) template requirement as well as four csu line build-out (lbo) filters of 0db, -7.5db, - 15db and -22.5db as required by fcc rules. it also pr ovides programmable transmit output pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions (the arbitrary pulse generator s are available for both t1 and e1, in short-haul configuration). the operation and configuration of the xrt83vl38 can be controlled through a microprocessor host interface (parallel or serial) or hardware control. master clock generator using a variety of external clock sources, the on-chi p frequency synthesizer generat es the t1 (1.544mhz) or e1 (2.048mhz) master cloc ks necessary for the transmit pulse shaping and receive clock recovery circuit. there are two master clock inputs mclke1 and mclkt1. in systems where both t1 and e1 master clocks are available these clocks can be connected to the respecti ve pins. all channels of a given xrt83vl38 must be operated at the same clock rate, either t1, e1 or j1 modes. in systems that have only one master cl ock source available (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. t1 or e1 master clocks can be generated from a single 1.544mhz or 2.048mhz external clock under the control of cl ksel[2:0] inputs according to table 1 . n ote : eqc[4:0] determi ne the t1/e1 operating mode. see table 5 for details. f igure 4. t wo i nput c lock s ource f igure 5. o ne i nput c lock s ource mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz 2.048mhz +/-50ppm 1.544mhz +/-50ppm two input clock sources mclke1 mclkt1 mclkout 1. 544mhz or 2. 048mhz one input clock source input clock options 1.544mhz 2.048mhz or
xrt83vl38 24 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 in host mode the programming is achieved through the corr esponding interface control bits, the state of the clksel[2:0] control bits an d the state of the mclkra te interface control bit. receiver receiver input at the receiver input, a cable attenuated ami signal can be coupled to the receiver through a capacitor or a 1:1 transformer. the input signal is first applied to a se lective equalizer for signal conditioning. the maximum equalizer gain is up to 36db for t1 and 43db for e1 modes. the equalized signal is subsequently applied to a peak detector which in turn controls t he equalizer settings and the data slicer. the slicer threshold for both e1 and t1 is typically set at 50% of the peak amplitude at the equalizer output. after the slicers, the digital representation of the ami signals are applied to t he clock and data recovery circuit. the recovered data subsequently goes through the jitter attenuator and decoder (if selected) for hdb3 or b8zs decoding before being applied to the rpos_n/rdata_n and rneg_n/lcv_n pins. clock recovery is accomplished by a digital phase-locked loop (dpll) which does not require any ex ternal components and can tolerate high levels of input jitter that meets or exceeds the itu-g.823 and tr-tsy000499 standards. t able 1: m aster c lock g enerator mclke1 k h z mclkt1 k h z clksel2 clksel1 clksel0 mclkrate m aster c lock k h z 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544
xrt83vl38 25 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator receive monitor mode in applications where monitor mode is desired, the equa lizer can be configured in a gain mode which handles input signals attenuated resistively up to 29db, along with 0 to 6db cable attenuation for both t1 and e1 applications, refer to table 5 for details. this feature is available in both hardware and host modes. receiver loss of signal (rlos) for compatibility with itu g.775 require ments, the rlos monitoring func tion is implemen ted using both analog and digital detection schemes. if the analog rlos condition occurs, a digital detector is activated to count for 32 consecutive zeros in e1 (4096 bits in ex tended los mode, exlos = ?1?) or 175 consecutive zeros in t1 before rlos is asserted. rlos is cleared when t he input signal rises +3db (b uilt in hysteresis) above the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more than 16 consecutive zeros for e1. in t1 mode, rlos is cleared when the input signal rises +3db (built in hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more than 100 consecutive zeros in the data stream. when lo ss of signal occurs, rlos register indication and register status will change . if the rlos register enabl e is set high (enabled), t he alarm will trigger an interrupt causing the interrupt pin ( int ) to go low. once the alarm status re gister has been read, it will automatically reset upon read (rur), and the int pin will return high. analog rlos setting the receiver inputs to -15db t1/e1 short haul mode by setting the receiver inputs to -15db t1/e1 short haul mode, the equalizer will detect the in coming amplitude and make adjustments by adding gain up to a maxi mum of +15db normalizing the t1/e1 input signal. n ote : this is the only setting that refers to cabl e loss (frequency), not flat loss (resistive). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+15db), the receiver will declare rlos if the signal is atte nuated by an additi onal -9db. the total cable lo ss at rlos declaration is typically -24db (-15db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, the rlos will typically clear at a total cable atten uation of -21db. see figure 6 for a simplified diagram. setting the receiver inputs to -29db t1/e1 gain mode by setting the receiver in puts to -29db t1/e1 gain mo de, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +29db normalizing the t1/e1 input signal. n ote : this is the only setting that refers to flat loss (resi stive). all other modes refer to cable loss (frequency). f igure 6. s implified d iagram of -15db t1/e1 s hort h aul m ode and rlos c ondition normalized up to +15db max normalized up to +15db max declare los clear los -9db +3db clear los declare los +3db -9db
xrt83vl38 26 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+29db), the receiver will declare rlos if the signal is atte nuated by an additi onal -9db. the total cable lo ss at rlos declaration is typically -38db (-29db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, th e rlos will typically clear at a to tal flat loss of -35db. see figure 7 for a simplified diagram. setting the receiver inputs to -36db t1/e1 long haul mode by setting the receiver inputs to - 36db t1/e1 long haul mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +36db normalizing the t1 input signal. this setting refers to cable loss (frequency), not fl at loss (resistive). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+36 db), the receiver will declare rlos if the signal is attenuated by an additional -9db. the total cable loss at rlos declaratio n is typically -45db (-36db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, the rl os will typically clear at a total cable attenuation of -42db. see figure 8 for a simplified diagram. e1 extended rlos e1: setting the receiver inputs to extended rlos by setting the receiver inputs to extended rlos, the equalizer will detect the incoming am plitude and make adjustments by adding gain up to a maximum of +43db normalizing the e1 input signal. this setting refers to f igure 7. s implified d iagram of -29db t1/e1 g ain m ode and rlos c ondition f igure 8. s implified d iagram of -36db t1/e1 l ong h aul m ode and rlos c ondition normalized up to +29db max normalized up to +29db max declare los clear los -9db +3db clear los declare los +3db -9db normalized up to +36db max normalized up to +36db max declare los clear los -9db +3db clear los declare los +3db -9db
xrt83vl38 27 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator cable loss (frequency), not flat loss (resistive). once the e1 input signal has been normalized to 0db by adding the maximum gain (+43db), the receiv er will declare rlos if the signal is attenuated by an additional -9db. the total cable loss at rlos declaratio n is typically -52db (-43db + -9db). a 3db hysteresis was designed so that transients will not trigge r the rlos to clear. therefore, the rlos will typically clear at a total cable attenuation of -49db. see figure 9 for a simplified diagram. receive hdb3/b8zs decoder the decoder function is available in both hardware and host modes on a per channel basis by controlling the tneg_n/codes_n pin or the codes_n interface bit. the de coder function is only active in single-rail mode. when selected, receive data in this mode will be decoded according to hdb3 rules for e1 and b8zs for t1 systems. bipolar violations that do not conform to the coding scheme will be reported as line code violation at the rneg_n/lcv_n pin of each channel. the length of the lcv pulse is one rclk cycle for each code violation. in e1mode only, an excessive number of zeros in the receive data stream is also reported as an error at the same output pin. if ami decodi ng is selected in single rail mode, ev ery bipolar violation in the receive data stream will be reported as an error at the rneg_n/lcv_n pin. recovered clock (rclk) sampling edge this feature is available in both hardware and host modes on a global basis. in host mode, the sampling edge of rclk output can be changed through the interf ace control bit rclke. if a ?1? is written in the rclke interface bit, receive data output at rpos_n/rdata_n and rneg_n/lcv_n are updated on the falling edge of f igure 9. s implified d iagram of e xtended rlos mode (e1 o nly ) normalized up to +45db max normalized up to +45db max declare los clear los -9db +3db clear los declare los +3db -9db
xrt83vl38 28 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 rclk for all eight channels. writing a ?0 ? to the rclke register, updates the re ceive data on the rising edge of rclk. in hardware mode the same feature is available under the control of the rclke pin. jitter attenuator to reduce phase and frequency jitter in the recovered cl ock, the jitter attenuator can be placed in the receive signal path. the jitter attenuator uses a data fifo (first in first out) with a progra mmable depth that can vary between 2x32 and 2x64. the jitter attenuator can also be placed in the transmit signal path or disabled altogether depending upon system requirements. the jitter attenuator, other than using the master clock as reference, requires no external components. with the ji tter attenuator selected, the typical throughput delay from input to output is 16 bits for 32 bit fifo size or 32 bits for 64 bit fifo size. when the read and write pointers of the fifo in the jitter attenuator are within tw o bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. when this situation occurs, the jitter a ttenuator will not attenuate input jitter until the read/write pointer's position is outside the two bits window. under normal condition, the jitte r transfer characteristic meets the narrow bandwidth requirement as specified in itu- g.736, itu- i.431 and at&t pub 62411 standards. in t1 mode the jitter attenuator bandwidth is always set to 3hz. in e1 mode, the bandwidth can be reduced through the jabw control signal. when jabw is set ?hi gh? the bandwidth of the jitter attenuator is reduced from 10hz to 1.5hz. under this condition the fifo length is automatically set to 64 bits and the 32 bits fifo length will not be available in this mode. jitter attenuat or controls are available on a per channel basis in the host mode and on a global basis in the hardware mode. gapped clock (ja must be e nabled in the transmit path) the xrt83vl38 liu is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. as the higher data rates are de-multipl exed down to t1 or e1 data, stuffing bits are removed which can leave gaps in the incoming data stream. if th e jitter attenuator is enabled in the transmit path, the 32-bit or 64-bit fifo is used to smooth the gapped cl ock into a steady t1 or e1 output. the maximum gap width of the 8-channel liu is shown in table 2 . n ote : if the liu is used in a loop timing system, the jitter attenuator should be enabled in the receive path. f igure 10. r eceive c lock and o utput d ata t iming t able 2: m aximum g ap w idth for m ultiplexer /m apper a pplications fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui rclk r rclk f rclk rpos or rneg r dy r ho
xrt83vl38 29 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator arbitrary pulse generator for t1 and e1 the arbitrary pulse generator divides the pulse into eigh t individual segments. each segment is set by a 7-bit binary word by programming the appropriate channel re gister. this allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. the msb (bit 7) is a sign-bit. if the sign-bit is set to ?1?, the segment will move in a posit ive direction relative to a flat line (zer o) condition. if this sign-bit is set to ?0?, the segment will move in a negative direction relative to a flat line condition. a pulse with numbered segments is shown in figure 11 . n ote : by default, the arbitrary segments are programmed to 0x00h. the transmitter outputs will result in an all zero pattern to the line. for e1 arbitrary mode, see global register 0xc0h. transmitter digital data format both the transmitter and receiver can be configured to operate in dual or single-rail data formats. this feature is available under both hardware and host control modes, on a global basis. the dual or single-rail data format is determined by the state of the sr/ dr pin in hardware mode or sr/ dr interface bit in the host mode. in single-rail mode, transmit clock and nrz data are app lied to tclk_n and tpos_n/tdata_n pins respectively. in single-rail and hardware mode the tneg_n/codes_n input can be used as the codes function. with tneg_n/codes_n tied ?low?, hdb3 or b8zs encoding and decoding are enabled for e1 and t1 modes respectively. with tneg_n/codes_n tied ?high?, the ami coding scheme is selected. in both dual or single- rail modes of operations, the transmitter converts digita l input data to a bipolar format before being transmitted to the line. transmit clock (tclk) sampling edge serial transmit data at tpos_n/tdata_n and tneg_n/codes_n are clocked into the xrt83vl38 under the synchronization of tclk_n. with a ?0 ? written to the tclke interface bit, or by pulling the tclke pin ?low?, input data is sampled on t he falling edge of tclk_n. the sampling edge is in verted with a ?1? written to tclke interface bit, or by connec ting the tclke pin ?high?. f igure 11. a rbitrary p ulse s egment a ssignment 1 2 3 4 5 6 7 8 segment register 1 0xn8 2 0xn9 3 0xna 4 0xnb 5 0xnc 6 0xnd 7 0xne 8 0xnf
xrt83vl38 30 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 transmit hdb3/b8zs encoder the encoder function is available in both hardware and host modes on a per channel basis by controlling the tneg_n/codes_n pin or codes interface bit. the encoder is only available in singl e-rail mode. in e1 mode and with hdb3 encoding selected, any sequence with four or more consecutive zeros in the input serial data from tpos_n/tdata_n, will be remo ved and replaced with 000v or b00v, where ?b? indicates a pulse conforming with the bipolar rule and ?v? representing a pulse violating the rule. an example of hdb3 encoding is shown in table 3 . in a t1 system, an input dat a sequence with eight or mo re consecutive zeros will be removed and replaced using the b8zs encoding rule. an example of bipolar with 8 zero substitution (b8zs) encoding scheme is shown in table 4 . writing a ? 1 ? into the codes_n interface bit or connecting the tneg_n/ codes_n pin to a ?high? le vel selects the ami coding for both e1 or t1 systems. f igure 12. t ransmit c lock and i nput d ata t iming t able 3: e xamples of hdb3 e ncoding n umber of pulse before next 4 zeros n ext 4 bits input 0000 hdb3 (case1) odd 000v hdb3 (case2) even b00v t able 4: e xamples of b8zs e ncoding c ase 1 p receding p ulse n ext 8 b its input + 00000000 b8zs 000vb0vb ami output + 000+ -0- + c ase 2 input - 00000000 b8zs 000vb0vb ami output - 000- +0+ - tclk r tclk f tclk tpos/tdata or tneg t su t ho
xrt83vl38 31 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator driver failure monitor (dmo) the driver monitor circuit is used to detect transmit driv er failure by monitoring the activities at ttip and tring outputs. driver failure may be caused by a short circui t in the primary transformer or system problems at the transmit input. if the transmitter of a channel has no output for more than 128 clock cycles, the corresponding dmo pin goes ?high? and remains ?high? until a valid transmit pulse is detected. in host mode, the failure of the transmit channel is reported in the corresponding interface bit. if the dmoi e bit is also enabled, any transition on the dmo interface bit will ge nerate an interrupt. th e driver failure monitor is supported in both hardware and host modes on a per channel basis. transmit pulse shaper & line build out (lbo) circuit the transmit pulse shaper circuit uses the high speed clock from the master timing generator to control the shape and width of the transmitted pulse. the internal high-speed timing generator eliminates the need for a tightly controlled transmit cl ock (tclk) duty cycle. with the jitter at tenuator not in the transmit path, the transmit output will generat e no more than 0.025unit interv al (ui) peak-to-peak jitter. in hardware mode, the state of the a[4:0]/eqc[4:0] pins determine the transmit pulse shape for all eight channels. in host mode transmit pulse shape can be controlled on a per channe l basis using the interface bits eqc[4:0]. the chip supports five fixed transmit pulse settings for t1 shor t-haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes (the arbitrary pulse generators are available for both t1 and e1). transmit line build-outs for t1 long-haul application are supported from 0db to -22.5db in three 7.5db steps. the choice of the transmit pulse shape and lbo under the control of the interface bits are summarized in table 5 . for csu lbo transmit pulse design information, refer to ansi t1.403-1993 network- to-customer installation specification, annex-e. n ote : eqc[4:0] determine t he t1/e1 operating mode of the xrt83vl38. when eqc4 = ?1? and eqc3 = ?1?, the xrt83vl38 is in the e1 mode, otherwise it is in the t1/j 1 mode. for details on how to enable the e1 arbitrary mode, see global register 0xc0h. t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings eqc4 eqc3 eq c2 eqc1 eqc0 e1/t1 m ode & r eceive s ensitivity t ransmit lbo c able c oding 0 0 0 0 0 t1 long haul/36db 0db 100 ? / tp b8zs 0 0 0 0 1 t1 long haul/36db -7.5db 100 ? / tp b8zs 0 0 0 1 0 t1 long haul/36db -15db 100 ? / tp b8zs 0 0 0 1 1 t1 long haul/36db -22.5db 100 ? / tp b8zs 0 0 1 0 0 t1 long haul/45db 0db 100 ? / tp b8zs 0 0 1 0 1 t1 long haul/45db -7.5db 100 ? / tp b8zs 0 0 1 1 0 t1 long haul/45db -15db 100 ? / tp b8zs 0 0 1 1 1 t1 long haul/45db -22.5db 100 ? / tp b8zs 0 1 0 0 0 t1 short haul/15db 0-133 ft./ 0.6db 100 ? / tp b8zs 0 1 0 0 1 t1 short haul/15db 133-266 ft./ 1.2db 100 ? / tp b8zs 0 1 0 1 0 t1 short haul/15db 266-399 ft./ 1.8db 100 ? / tp b8zs 0 1 0 1 1 t1 short haul/15db 399-533 ft./ 2.4db 100 ? / tp b8zs 0 1 1 0 0 t1 short haul/15db 533-655 ft./ 3.0db 100 ? / tp b8zs
xrt83vl38 32 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 0 1 1 0 1 t1 short haul/15db arbitrary pulse 100 ? / tp b8zs 0 1 1 1 0 t1 gain mode/29db 0-133 ft./ 0.6db 100 ? / tp b8zs 0 1 1 1 1 t1 gain mode/29db 133-266 ft./ 1.2db 100 ? / tp b8zs 1 0 0 0 0 t1 gain mode/29db 266-399 ft./ 1.8db 100 ? / tp b8zs 1 0 0 0 1 t1 gain mode/29db 399-533 ft./ 2.4db 100 ? / tp b8zs 1 0 0 1 0 t1 gain mode/29db 533-655 ft./ 3.0db 100 ? / tp b8zs 1 0 0 1 1 t1 gain mode/29db arbitrary pulse 100 ? / tp b8zs 1 0 1 0 0 t1 gain mode/29db 0db 100 ? / tp b8zs 1 0 1 0 1 t1 gain mode/29db -7.5db 100 ? / tp b8zs 1 0 1 1 0 t1 gain mode/29db -15db 100 ? / tp b8zs 1 0 1 1 1 t1 gain mode/29db -22.5db 100 ? / tp b8zs 1 1 0 0 0 e1 long haul/36db itu g.703/arbitrary 75 ? coax hdb3 1 1 0 0 1 e1 long haul/36db itu g.703/arbitrary 120 ? tp hdb3 1 1 0 1 0 e1 long haul/43db itu g.703/arbitrary 75 ? coax hdb3 1 1 0 1 1 e1 long haul/43db itu g.703/arbitrary 120 ? tp hdb3 1 1 1 0 0 e1 short haul itu g.703/arbitrary 75 ? coax hdb3 1 1 1 0 1 e1 short haul itu g.703/arbitrary 120 ? tp hdb3 1 1 1 1 0 e1 gain mode itu g.703/arbitrary 75 ? coax hdb3 1 1 1 1 1 e1 gain mode itu g.703/arbitrary 120 ? tp hdb3 t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings eqc4 eqc3 eq c2 eqc1 eqc0 e1/t1 m ode & r eceive s ensitivity t ransmit lbo c able c oding
xrt83vl38 33 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator transmit and receive terminations the xrt83vl38 is a versatile liu th at can be programmed to use one bill of materials (bom) for worldwide applications for t1, j1 and e1. for specific applications the internal terminations can be disabled to allow the use of existing components and/or designs. receiver (channels 0 - 7) i nternal r eceive t ermination m ode in hardware mode, rxtsel (pin 83) can be tied ?high? to select internal termination mode for all receive channels or tied ?low? to select external termination mode. individual channel control can only be done in host mode. by default the xrt83vl38 is set for ex ternal termination mode at power up or at hardware reset. in host mode, bit 7 in the appropriate channel register, ( table 24, ?microprocessor register #1, bit description,? on page 59 ), is set ?high? to select the internal termination mode for that specific receive channel. if the internal termination mode (rxtsel = ?1?) is selected, the effective impedance for e1, t1 or j1 can be achieved either with an internal resistor or a combin ation of internal and exter nal resistors as shown in table 7 . n ote : in hardware mode, pins rxres[1:0] control all channels. t able 6: r eceive t ermination c ontrol rxtsel rx termination 0 external 1 internal f igure 13. s implified d iagram for the i nternal r eceive and t ransmit t ermination m ode t1 ttip tring 5 8 1:2 75 ?? , 100 ? 110 ?? ? or 120 ?? 4 1 0.68 ? f r int r int ttip tring tx line driver t2 rtip rring 1 4 1:1 8 5 rtip rring rx equalizer r int channel _n tpos tneg tclk rpos rneg rclk 75 ?? , 100 ? 110 ?? ? or 120 ??
xrt83vl38 34 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 figure 14 is a simplified diagram for t1 (100 ? ) in the external receive and transmit termination mode. figure 15 is a simplified diagram for e1 (75 ? ) in the external receive and internal transmit termination mode. t able 7: r eceive t erminations rxtsel tersel1 tersel0 rxres1 rxres0 r ext r int m ode 0 x x x x r ext ? t1/e1/j1 1 0 0 0 0 ? 100 ? t1 1 0 1 0 0 ? 110 ? j1 1 1 0 0 0 ? 75 ? e1 1 1 1 0 0 ? 120 ? e1 1 0 0 0 1 240 ? 172 ? t1 1 0 1 0 1 240 ? 204 ? j1 1 1 0 0 1 240 ? 108 ? e1 1 1 1 0 1 240 ? 240 ? e1 1 0 0 1 0 210 ? 192 ? t1 1 0 1 1 0 210 ? 232 ? j1 1 1 0 1 0 210 ? 116 ? e1 1 1 1 1 0 210 ? 280 ? e1 1 0 0 1 1 150 ? 300 ? t1 1 0 1 1 1 150 ? 412 ? j1 1 1 0 1 1 150 ? 150 ? e1 1 1 1 1 1 150 ? 600 ? e1 f igure 14. s implified d iagram for t1 in the e xternal t ermination m ode (rxtsel= 0 & txt- sel= 0) ? ttip tring rtip rring xrt83vl 38 liu 100 ? 100 ? 100 ? 1:2 1:1 3. 1 ? 3.1 0.68uf
xrt83vl38 35 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator transmitter (channels 0 - 7) t ransmit t ermination m ode in hardware mode, txtsel (pin 84) can be tied ?high? to select internal termination mode for all transmit channels or tied ?low? for external terminatio n. individual channel control can be done only in host mode. in host mode, bit 6 in the appropriate register for a given chan nel is set ?high? to select the internal termination mode for that specific transmit channel, see table 24, ?microprocessor register #1, bit description,? on page 59 . in internal mode, no external resistors are used. an external capacitor of 0.68 ? f is used for proper operation of the internal termination circuitry, see figure 13 . e xternal t ransmit t ermination m ode by default the xrt83vl38 is set for external termination mode at power up or at hardware reset. when external transmit termination mode is selected, the internal termination circuitry is disabled. the value of the external resistors is chos en for a specific application. figure 14 is a simplified block diagram for t1 (100 ? ) in the external receive and transmit termination mode. figure 15 is a simplified block diagram for e1 (75 ? ) in the external receive termination and internal transmit termination mode. table 9 summarizes the transmit terminations. f igure 15. s implified d iagram for e1 in e xternal r eceive t ermination m ode (rxtsel= 0) and i nternal t ransmit t ermination m ode (txtel= 1) t able 8: t ermination s elect c ontrol tersel1 tersel0 termination 0 0 100 ? 0 1 110 ? 1 0 75 ? 1 1 120 ? ttip tring rtip rring 75 ? xrt83vl 38 liu 75 ? 75 ? 1: 2 1: 1 0.68uf
xrt83vl38 36 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 redundancy applications telecommunication system de sign requires signal integr ity and reliability. when a t1/e1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivi ty to a backplane without losing data. system designers can achieve this by implementing common redundancy schemes with the xrt83vl38 line interface unit (liu). the xrt83vl38 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. these features allow system designers to implement re dundancy applications th at ensure reliability. the internal impedance mode eliminates the need for exte rnal relays when using the 1:1 and 1+1 redundancy schemes. t able 9: t ransmit t erminations tersel1 tersel0 txtsel r int ? n (turns ratio) r ext ? c ext 0= external set by control bits n, r ext , and c ext are suggested settings 1= internal t1 100 ? 0 0 0 0 ? 2 3.1 ? 0 0 0 1 12.5 ? 2 0 ? 0.68 ? f j1 110 ? 0 1 0 0 ? 2 3.1 ? 0 0 1 1 13.75 ? 2 0 ? 0.68 ? f e1 75 ? 1 0 0 e1 external transmit termination not supported 1 0 1 9.4 ? 2 0 ? 0.68 ? f e1 120 ? 1 1 0 e1 external transmit termination not supported 1 1 1 15 ? 2 0 ? 0.68 ? f
xrt83vl38 37 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator programming considerations in many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter on/off switching. in host mode, there are two bits in register 130 (82h) th at control the transmitter outputs and the rx line impedance select, txoncntl (bit 7) and tercntl (bit 6). setting bit-7 (txoncntl) to a ?1? transfers the cont rol of the transmit on/off function to the txon_n hardware control pins. (pins 90 through 93 and pins 169 thro ugh 172). the txon is used to tri-state the transmit outputs when used in a redundancy application. setting bit-6 (tercntl) to a ?1? transfers the contro l of the rx line impedance select (rxtsel) to the rxtsel hardware control pin (pin 83). either mode works well with redundancy applications. the user can determine wh ich mode has the fastest switching time for a unique application. typical redundancy schemes n 1:1 one backup card for every primary card (facility protection) n 1+1 one backup card for every primary card (line protection) n n+1one backup card for n primary cards 1:1 redundancy a 1:1 facility protection redundancy scheme has one backup card for every primary ca rd. when using 1:1 redundancy, the backup card has its transmitters tri-stat ed and its receivers in high impedance. this eliminates the need for external re lays and provides one bill of materials for all inte rface modes of operat ion. the transmit and receive sections of the liu device are described separately. 1+1 redundancy a 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on the backup card are monitoring the receiver inputs. ther efore, the receivers on both cards need to be active. the transmit outputs require no external resistors. t he transmit and receive sections of the liu device are described separately. transmit 1:1 & 1+1 redundancy for 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for internal impedance mode. the transmitters on the backup card should be tri-stated. select the appropriate impedance for the desired mode of operation, t1/e1/j1 . a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted.
xrt83vl38 38 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 receive 1:1 & 1+1 redundancy for 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for internal impedance mode. the receivers on the backup card should be pr ogrammed for external impedance mode. since there is no external resistor in th e circuit, the receivers on the backup ca rd will be high impedan ce. this key design feature eliminat es the need for relays a nd provides one bill of materials fo r all interface mo des of operation. select the impedance for the desired mode of operatio n, t1/e1/j1. to swap the pr imary card, se t the backup card to internal impedance mode, then the primary card to external impedance mode. see figure 17 for a simplified block diagram of the receive se ction for a 1:1 and 1+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 16. s implified b lock d iagram of the t ransmit s ection for 1:1 & 1+1 r edundancy f igure 17. s implified b lock d iagram - r eceive s ection for 1:1 and 1+1 r edundancy t1/e1 line backplane interface primary card backup card xrt83vl38 xrt83vl38 tx tx line interface card 0.68 ? f 0.68 ? f txtsel=1, internal txtsel=1, internal 1:2 rxtsel=0, external rxtsel=1, internal backplane interface primary card backup card xrt83vl38 xrt83vl38 rx line interface card t1/e1 line rx 1:1
xrt83vl38 39 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator n+1 redundancy n+1 redundancy has one backup card for n primary card s. due to impedance mismat ch and signal contention, external relays are necessary when using this redundancy scheme. the advantage of relays is that they create complete isolation between the primary cards and the ba ckup card. this allows all transmitters and receivers on the primary cards to be configur ed in internal im pedance mode, providing one bill of materials for all interface modes of operation. the transmit and receive sections of the xrt83vl38 are described separately. transmit for n+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode providing one bill of materials for t1/e 1/j1. the transmitters on the backup card do not have to be tri-stated. to swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. a 0.68 ? f capacitor is used in series wit h ttip for blocking dc bias. see figure 18 for a simplified block diagram of the transmit section for an n+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 18. s implified b lock d iagram - t ransmit s ection for n+1 r edundancy backplane interface primary card xrt83vl38 tx line interface card 0.68 ? f t1/e1 line primary card xrt83vl38 tx primary card xrt83vl38 tx backup card xrt83vl38 tx t1/e1 line t1/e1 line txtsel=1, internal txtsel=1, internal txtsel=1, internal txtsel=1, internal 1:2 1:2 1:2 0.68 ? f 0.68 ? f 0.68 ? f
xrt83vl38 40 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 receive for n+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. the receivers on the backup card should be programmed for external impedance mode. since there is no external resistor in the circuit, th e receivers on the backup card will be hi gh impedance. select the impedance for the desired mode of operation, t1/e1/j1. to swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. see figure 19 . for a simplified block diagram of the receive section for a n+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 19. s implified b lock d iagram - r eceive s ection for n+1 r edundancy backplane interface primary card xrt83vl38 rx line interface card primary card xrt83vl38 rx primary card xrt83vl38 rx backup card xrt83vl38 rx rxtsel=1, internal rxtsel=1, internal rxtsel=1, internal rxtsel=1, external t1/e1 line t1/e1 line t1/e1 line 1:1 1:1 1:1
xrt83vl38 41 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator pattern transmit and detect function several test and diagnostic patterns can be generated and detected by the chip. in hardware mode each channel can be independently programmed to transmit an all ones pattern by applying a ?high? level to the corresponding taos_n pin. in host mode, the three interface bits txtest[2:0] control the pattern generation and detection independently for each channel according to table 10 . transmit all ones (taos) this feature is available in both hardware and host modes. with the taos_n pin connected to a ?high? level or when interface bits txtest2=?1?, txtest1=?0? and txtest0=?1? the transmitter ignores input from tpos_n/tdata_n and tneg_n/codes_n pi ns and sends a continuous ami encoded all ?ones? signal to the line, using tclk_n clock as the reference. in addition, when the hardware pin and interface bit ataos is activated, the chip will au tomatically transmit the all ?ones? data from any channel that detects an rlos condition. this feature is not available on a pe r channel basis. tclk_n must not be tied ?low?. network loop code detection and transmission this feature is available in host mode only. when the interface bits txtest2=?1?, txtest1=?1? and txtest0=?0? the chip is enabled to transmit the ?00001? network loop-up code from the selected channel requesting a loop-back condition from the remote te rminal. simultaneously setting the interface bits nlcde1=?0? and nlcde0=?1? enables the network loop-u p code detection in the receiver. if the ?00001? network loop-up code is detected in the receive data fo r longer than 5 seconds, the nlcd bit in the interface register is set indicating that the remote terminal has ac tivated remote loop-back and the chip is receiving its own transmitted data. when the interface bits txtest2=?1?, txtest1=?1? and txtest0=?1? the chip is enabled to transmit the network loop-down code (tldc) ?001? from the selected channel requesting the remote terminal the removal of the loop-back condition. in the host mode each channel is capable of monitoring the contents of the receive data for the presence of loop-up or loop-down code from the remote terminal. in the host mode the two interface bits nlcde[1:0] control the loop-code detection independently for each channel according to table 11 . setting the interface bits to nlcde1=?0? and nlcde0=?1? activates the detection of the loop-up code in the receive data. if the ?00001? network loop-up code is detected in the receive data for longer than 5 seconds, the nlcd interface bit is set to ?1? and stays in this st ate for as long as the receiver continues to receive the t able 10: p attern transmission control txtest2 txtest1 txtest0 t est p attern 0 x x none 1 0 0 tdqrss 1 0 1 taos 1 1 0 tluc 1 1 1 tldc t able 11: l oop -c ode d etection c ontrol nlcde1 nlcde0 condition 0 0 disable loop-code detection 0 1 detect loop-up code in receive data 1 0 detect loop-down code in receive data 1 1 automatic loop-code detection and remote loop-back activation
xrt83vl38 42 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 network loop-up code. in this mode if the nlcd interrupt is enabled, the chip will init iate an interrupt on every transition of nlcd. the host has the opti on to ignore the request from the re mote terminal, or to respond to the request and manually activate remote loop-back. the host can subsequently activate the detection of the loop-down code by setting nlcde1=?1 ? and nlcde0=?0?. in this case, re ceiving the ?001? loop-down code for longer than 5 seconds will set the nlcd bit to ?1? and if the nlcd interrupt is enab led, the chip will initiate an interrupt on every transition of nlcd. the host can respond to the request from the remote terminal and remove loop-back condition. in the manual netw ork loop-up (nlcde1=?0? and nlcde0=?1?) and loop- down (nlcde1=?1? and nlcde0=?0?) co de detection modes, the nlcd inte rface bit will be set to ?1? upon receiving the correspond ing code in excess of 5 seconds in the rece ive data. the chip will in itiate an interrupt any time the status of the nlcd bit changes an d the network loop-code interrupt is enabled. in the host mode, setting the interface bits nlcde1=?1? and nlcde0=?1? enables the automatic loop-code detection and remote loop-back activation mode if, tx test[2:0] is not equal to ?110?. as this mode is initiated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to monitor the receive input data for the loop-up code. if the ?00001? network loop-up code is detected in the receive data for longer than 5 seconds in addition to the nlcd bit in the interface register being set, remote loop-back is automatically activated. the chip stays in remote loop-back even if it stops receiving the ?00001? pattern. after the chip detects the loop-up code, sets the nlcd bit and enters remote loop-back, it automatically starts monitoring the receive data for the loop-down code. in this mode however, the nlcd bit stays set even if the receiver stops receiving the loop-up code, which is an in dication to the host that the remote loop-back is still in effect. remote loop-back is removed if the chip detects the ?001? loop-down code for longer than 5 seconds. detecting the ?001? code also results in resetting the nlcd interf ace bit and initiating an interrupt. the remote loop-back can also be removed by taking the chip out of the automatic detection mode by programming it to operate in a diff erent state. the chip will not respond to remote loop-back request if local analog loop-back is activated locally. when programmed in automatic detection mode the nlcd interface bit stays ?high? for the whole time the remote loop-back is activated and initiates an interrupt any time the status of the nlcd bit changes provided the network loop-code interrupt is enabled. transmit and detect quasi-rand om signal source (tdqrss) each channel of xrt83vl38 includes a qrss pattern gen eration and detection block for diagnostic purposes that can be activated only in the host mode by setting the interface bits txtest2=?1?, txtest1=?0? and txtest0=?0?. for t1 systems, the qrss pattern is a 2 20 -1pseudo-random bit sequence (prbs) with no more than 14 consecutive zeros. for e1 systems, the qrss pattern is 2 15 -1 prbs with an inverted output. with qrss and analog local loop-back enabled simultan eously, and by monitoring the status of the qrpd interface bit, all main functional blocks within the transceiver can be verified. when the receiver achieves qrss sy nchronization with fewer than 4 errors in a 128 bits window, qrpd changes from ?low? to ?high?. after pattern synchronization, any bit erro r will cause qrpd to go ?low? for one clock cycle. if the qrpdie bit is enabled, any tran sition on the qrpd bit will generate an interrupt. with tdqrss activated, a bit error can be inserted in the transmitted qrss pattern by transitioning the insber interface bit from ?0? to ?1?. bipolar violation ca n also be inserted either in the qrss pattern, or input data when operating in the single-rail mode by transitioning t he insbpv interface bit from ?0? to ?1?. the state of insber and insbpv bits are sampled on the rising edge of the tclk_n. to insure the insertion of the bit error or bipolar violation, a ?0? should be writ ten in these bit locations before writing a ?1?.
xrt83vl38 43 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator loop-back modes the xrt83vl38 supports several loop-back modes under both hardware and host control. in hardware mode the two loop[1:0] pins control the loop-back f unctions for each channel independently according to table 12 . in host mode the loop-back functions are controlled by the three loop[2:0] interface bits. each channel can be programmed independently according to table 13 . local analog loop-back (aloop) with local analog loop-back activated, the transmit data at ttip and tring are looped-back to the analog input of the receiver. external inputs at rtip/rring in this mode are ignored while valid transmit data continues to be sent to the line. local analog loop-ba ck exercises most of the functional blocks of the xrt83vl38 including the jitter attenuator which can be se lected in either the transmit or receive paths. local analog loop-back is shown in figure 20 . in this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path. t able 12: l oop - back control in h ardware mode loop1 loop0 l oop - back m ode 0 0 none 0 1 analog 1 0 remote 1 1 digital t able 13: l oop - back control in h ost mode loop2 loop1 loop0 l oop - back m ode 0 x x none 1 0 0 dual 1 0 1 analog 1 1 0 remote 1 1 1 digital f igure 20. l ocal a nalog l oop - back signal flow rx data & clock recovery decoder tpos tneg tclk rclk rpos rneg tx encoder timing control ja ttip tring rtip rring
xrt83vl38 44 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 remote loop-back (rloop) with remote loop-back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using rclk as transmit timing. in this mode transmit clock and data are ignored, while rclk and re ceive data will continue to be available at their respective output pins. remote loop-back with jitter attenuator select ed in the receive path is shown in figure 21 . in the remote loop-back mode if the jitter attenuator is selected in the transmit path, the receive data from the clock and data recovery block is looped back to the trans mit path and is applied to the jitter attenuator using rclk as transmit timing. in this mode the transmit clo ck and data are also ignored, while rclk and received data will continue to be available at their respective output pins. remote loop-back wit h the jitter attenuator selected in the transmit path is shown in figure 22 . f igure 21. r emote l oop - back mode with jitter attenuator selected in receive path f igure 22. r emote l oop - back mode with jitter attenuator selected in t ransmit path tx decoder timing control rx data & clock recovery tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring ja tx decoder timing control rx clock & data recovery ja tpos tneg tclk rclk rpos rneg encoder ttip trin g rtip rrin g
xrt83vl38 45 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator digital loop-back (dloop) digital loop-back or local loop-back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder /decoder and jitter attenuator. in this mode, receive data and clock are ignored, bu t the transmit data will be sent to the lin e uninterrupted. this loop back feature allows users to configure the line interface as a pure jitter attenuator. the digital loop-back signal flow is shown in figure 23 . dual loop-back figure 24 depicts the data flow in dual-loopback. in this mo de, selecting the jitter attenuator in the transmit path will have the same result as plac ing the jitter attenuator in the receive path. in d ual loop-back mode the recovered clock and data from the line are looped back through the transmitter to the ttip and tring without passing through the jitter attenuator. the transmit clock a nd data are looped back through the jitter attenuator to the rclk and rpos/rdata and rneg pins. for proper operation of dual loop-back mode, tclk must be present. f igure 23. d igital l oop - back mode with jitter attenuator selected in t ransmit path f igure 24. s ignal flow in d ual loop - back mode tx decoder timing control rx data & clock recovery ja tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring tx decoder timing control rx data & clock recovery ja tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring
xrt83vl38 46 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 microprocessor interface the microprocessor interface can be accessed through a standard serial interface or a standard parallel microprocessor interface. the ser_ par pin is used to select between the two. by default, the chip is configured in the parallel micr oprocessor intera ce. for serial communication, this pin must be pulled ?high?. serial microprocessor interface block the serial microprocessor uses a standard 3-pin serial port with cs , sclk, and sdi for programming the liu. optional pins such as sdo, int , and reset allow the ability to read back cont ents of the regi sters, monitor the liu via an interrupt pin, and reset the liu to its default co nfiguration by pulling rese t "low" for more than 10 ? s. a simplified block diagram of the serial microprocessor is shown in figure 25 . s erial t iming i nformation the serial port requires 24 bits of data applied to the sdi (serial data input) pin. the serial microprocessor samples sdi on the rising edge of sclk (serial clock input). the data is not latched into the device until all 24 bits of serial data have been sampled. a timing diagram of the serial microprocessor is shown in figure 26 . n ote : for applications without a free running sclk, a minimum of 1 sclk pulse must be applied when cs is ?high?, befrore pulling cs ?low?. 24-b it s erial d ata i nput d escritption f igure 25. s implified b lock d iagram of the s erial m icroprocessor i nterface f igure 26. t iming d iagram for the s erial m icroprocessor i nterface serial microprocessor interface cs sdi sclk sdo reset int hw/host ser_par r/w addr[0] - addr[7] don't care data[0] - data[7] cs sdi sclk 8-bit address 8-bit data 7-bit don't care 1=read 0=write sdo data[0] - data[7] readback
xrt83vl38 47 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator the serial data input is sampled on the rising edge of sclk. in readback mode, the serial data output is updated on the falling edge of sclk. the serial data must be applied to the liu lsb fi rst. the 24 bits of serial data are described below. addr[7:0] (sclk1 - sclk8) the first 8 sclk cycles are used to provide the address to which a read or write operation will occur. addr[0] (lsb) must be sent to the liu first followed by addr[1] and so forth until all 8 address bits have been sampled by sclk. r/w (sclk9) the next serial bit applied to the liu informs the micropro cessor that a read or write operation is desired. if the r/w bit is set to ?0?, the microprocessor is configured for a write operation. if the r/w bit is set to ?1?, the microprocessor is configured for a read operation. d ummy b its (sclk10 - sclk16) the next 7 sclk cycles are used as dummy bits. seve n bits were chosen so that the serial interface can easily be divided into three 8-bit words to be complia nt with standard serial interf ace devices. the state of these bits are ignored and can hold either ?0? or ?1? during both read and write operations. data[7:0] (sclk17 - sclk24) the next 8 sclk cycles are used to provide the data to be written into the internal register chosen by the address bits. data[0] (lsb) must be sent to the liu firs t followed by data[1] and so forth until all 8 data bits have been sampled by sclk. once 24 sclk cycles have been completed, the liu holds the data until cs is pulled ?high? whereby, the serial microprocessor latc hes the data into the selected internal register. 8-b it s erial d ata o utput d escription the serial data output is updated on the falling edge of sclk17 - sclk24 if r/w is set to ?1?. data[0] (lsb) is provided on sclk17 to the sdo pin first followed by data[1] and so forth until all 8 data bits have been updated. the sdo pin allows the us er to read the contents stored in individual registers by providing the desired address on the sdi pin during the read cycle. f igure 27. t iming d iagram for the m icroprocessor s erial i nterface sdi addr 6 r/w addr 7 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t 21 t 22 t 23 t 24 t 25 t 26 t 28 t 29 t 31 don?t care (read mode) hi-z
xrt83vl38 48 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 parallel microprocesso r interface block the parallel microprocessor interfac e section supports communication bet ween the local microprocessor (p) and the liu. the xrt83vl38 supports an intel asyn chronous interface and motorola 68k asynchronous interface. the microprocessor interf ace is selected by the state of the pts[2:1] input pins. selecting the microprocessor interface is shown in table 15 . the xrt83vl38 uses multipurpose pins to configure the device appropriately. the local p configures the liu by writing data into specific addressable, on-chip read/ write registers. the microprocessor interface provides the signals which are required for a general purpose micropr ocessor to read or write data into these registers. the microprocessor interface also supports polled and interrupt driven environments. a simplified block diagram of the microprocessor is shown in figure 28 . t able 14: m icroprocessor s erial i nterface t imings ( t a = 25 0 c, v dd =3.3v 5% and load = 10 p f) s ymbol p arameter m in . t yp . m ax u nits t 21 cs low to rising edge of sclk 5 ns t 22 sdi to rising edge of sclk 5 ns t 23 sdi to rising edge of sclk hold time 5 ns t 24 sclk "low" time 20 ns t 25 sclk "high" time 20 ns t 26 sclk period 40 ns t 28 cs inactive time 40 ns t 29 falling edge of sclk to sdo valid time 5 ns t 31 rising edge of cs to high z 5 ns t able 15: s electing the m icroprocessor i nterface m ode pts[2:1] m icroprocessor m ode 0h (00) intel 68hc11, 8051, 80c188 (asynchronous) 1h (01) motorola 68k (asynchronous)
xrt83vl38 49 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t he m icroprocessor i nterface b lock s ignals the liu may be configured into different operating mo des and have its performance monitored by software through a standard microprocessor using data, address and control signals. these interface signals are described below in table 16 , table 17 , and table 18 . the microprocessor interface can be configured to operate in intel mode or motorola mode. when the microprocessor interface is operating in intel mode, some of the control signals function in a manner required by the intel 80xx family of microprocessors. likewise, when the microprocessor interface is operating in motorola mo de, then these control signals function in a manner as required by the motorola microprocessors. (for using a motorola 68k asynchronous processor, see figure 30 and table 20 ) table 16 lists and describes those microproce ssor interface signals whose role is constant across the two modes. table 17 describes the role of some of these signals when the microprocessor interface is operating in the intel mode. likewise, table 18 describes the role of these signals when the microprocessor interface is operating in the motorola power pc mode. f igure 28. s implified b lock d iagram of the m icroprocessor i nterface b lock t able 16: xrt83vl38 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes p in n ame t ype d escription pts[2:1] i microprocessor interface mode select input pins these two pins are used to specify the microprocessor interface mode. the relationship between the state of these two input pins, and the corresponding microprocessor mode is pre - sented in table 15 . data[7:0] i/o bi-directional data bus for register "read" or "write" operations. addr[7:0] i eight-bit address bus inputs the xrt83vl38 liu microprocessor interface uses a direct address bus. this address bus is provided to permit the user to select an on-chip register for read/write access. cs i chip select input this active low signal selects the microprocessor interface of the xrt83vl38 liu and enables read/write operations with the on-chip register locations. microprocessor interface wr_r/w rd_ds ale pts [2:1] rdy reset cs int addr[7:0] data[7:0]
xrt83vl38 50 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 i ntel m ode p rogrammed i/o a ccess (a synchronous ) if the liu is interfaced to an intel type p, then it should be configured to operate in the intel mode. intel type read and write operations are described below. intel mode read cycle whenever an intel-type p wishes to read the contents of a register, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. toggle the ale input pin "high". this step enables t he address bus input drivers, within the microproces - sor interface block of the liu. 4. the p should then toggle the ale pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. t able 17: i ntel mode : m icroprocessor i nterface s ignals xrt83vl38 p in n ame i ntel e quivalent p in t ype d escription ale ale i address-latch enable: this active high signal is used to latch the contents on the address bus addr[7:0]. the contents of the address bus are latched into the addr[7:0] inputs on the falling edge of ale. rd _ds rd i read signal: this active low input functions as the read signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a read oper - ation has been requested and begins the process of the read cycle. wr _r/ w wr i write signal: this active low input functions as the write signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a write operation has been requested and begins the process of the write cycle. rdy rdy o ready output: this active low signal is provided by the liu device. it indicates that the current read or write cycle is co mplete, and the liu is waiting for the next command. t able 18: m otorola m ode : m icroprocessor i nterface s ignals xrt83vl38 p in n ame m otorola e quivalent p in t ype d escription ale as i address strobe: this active high signal is used to latch the contents on the address bus addr[7:0]. the contents of the address bus are latched into the addr[7:0] inputs on the falling edge of as. wr _r/ w r/ w i read/ write : this input pin from the local p is used to inform the liu whether a read or write operation has been requested. when this pin is pulled ?high?, ds will initiate a read o peration. when this pin is pulled ?low?, ds will initiate a write operation. rd _ds ds i data strobe: this active low input functions as the read or write signal from the local p dependent on the state of r/ w . when ds is pulled ?low? (if cs is ?low?) the liu begins the read or write operation. rdy dtack o data transfer acknowledge: this active low signal is provided by the liu device. it indicates that the current read or write cycle is complete, and the liu is waiting for the next command.
xrt83vl38 51 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 5. next, the p should indicate that this curren t bus cycle is a read operation by toggling the rd input pin "low". this action also enables the bi-direc tional data bus output drivers of the liu. 6. after the p toggles the read si gnal "low", the liu will toggle the rdy output pin "low". the liu does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next com - mand. 7. after the p detects the rdy signal and has read the data, it can terminate the read cycle by toggling the rd input pin "high". n ote : ale can be tied ?high? if this signal is not available. the intel mode write cycle whenever an intel type p wishes to write a byte or word of data into a register withi n the liu, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. toggle the ale input pin "high". this step enables t he address bus input drivers, within the microproces - sor interface block of the liu. 4. the p should then toggle the ale pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. the p should then place the byte or word that it inte nds to write into the target register, on the bi-direc - tional data bus data[7:0]. 6. next, the p should indicate that this curren t bus cycle is a write operation by toggling the wr input pin "low". this action also enables the bi-direc tional data bus input drivers of the liu. 7. after the p toggles the write signal "low", the liu will toggle the rdy output pin "low". the liu does this in order to inform the p that the data has been written into the internal register location, and that it is ready for the next command. n ote : ale can be tied ?high? if this signal is not available. the intel read and write timing diagram is shown in figure 29 . the timing specifications are shown in table 19 . f igure 29. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations cs addr[10:0] ale = 1 data[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address
xrt83vl38 52 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 m otorola m ode p rogrammed i/o a ccess (a synchronous ) if the liu is interfaced to a motorola type p, it should be configured to operate in the motorola mode. motorola type programmed i/o read and write operations are described below. motorola mode read cycle whenever a motorola type p wishes to read the contents of a register, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. the p should then toggle the as pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate th at this current bus cycle is a read operation by pulling the r/ w input pin "high". 5. toggle the ds input pin "low". this action enables the bi-directional data bus output drivers of the liu. 6. after the p toggles the ds signal "low", the liu will toggle the dtack output pin "low". the liu does this in order to inform the p that th e data is available to be read by the p , and that it is ready for the next command. 7. after the p detects the dtack signal and has read the data, it can terminate the read cycle by toggling the ds input pin "high". motorola mode write cycle whenever a motorola type p wishes to write a byte or word of data into a register within the liu, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. the p should then toggle the as pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate th at this current bus cycle is a write operation by pulling the r/ w input pin "low". 5. toggle the ds input pin "low". this action enables the bi-directional data bus output drivers of the liu. 6. after the p toggles the ds signal "low", the liu will toggle the dtack output pin "low". the liu does this in order to inform the p that the data has been wr itten into the internal register location, and that it is ready for the next command. t able 19: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 65 - ns t 2 rd assert to rdy assert - 90 ns na rd pulse width (t 2 ) 90 - ns t 3 cs falling edge to wr assert 65 - ns t 4 wr assert to rdy assert - 90 ns na wr pulse width (t 4 ) 90 - ns
xrt83vl38 53 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 7. after the p detects the dtack signal and has read the data, it can terminate the read cycle by toggling the ds input pin "high". the motorola read and write timing diagram is shown in figure 30 . the timing specifications are shown in table 20 . microprocessor register tables the microprocessor interface consists of 256 addressable locations. each channel uses 16 dedicated 8 byte registers for independent programming and control. there ar e four additional registers for global control of all channels and two registers for device identification and revision numbers. the remaining registers are for factory test and future expansion. the control regist er map and the function of the individual bits are summarized in table 21 and table 22 respectively. f igure 30. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 20: m otorola 68k m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds (pin rd _ds) assert 65 - ns t 2 ds assert to dtack assert - 90 ns na ds pulse width (t 2 ) 90 - ns t 3 cs falling edge to as (pin ale) falling edge 0 - ns cs addr[7:0] as data[7:0] rd _ds wr _r/w rdy _dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 motorola asychronous mode valid address valid address t 3 t 3 t 1 t 2
xrt83vl38 54 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 21: m icroprocessor r egister a ddress r egister n umber r egister a ddress f unction hex binary 0 - 15 0x00 - 0x0f 00000000 - 00001111 channel 0 control registers 16 - 31 0x10 -0x1f 00010000 - 00011111 channel 1 control registers 32 - 47 0x20 - 0x2f 00100000 - 00101111 channel 2 control registers 48 - 63 0x30 - 0x3f 00110000 - 00 111111 channel 3 control registers 64 - 79 0x40 - 0x4f 01000000 - 01001111 channel 4 control registers 80 - 95 0x50 - 0x5f 01010000 - 01011111 channel 5 control registers 96-111 0x60 - 0x6f 01100000 - 01101111 channel 6 control registers 112 - 127 0x70 - 0x7f 01110000 - 011 11111 channel 7 control registers 128 - 131 0x80 - 0x83 10000000 - 10000011 command control registers for all 8 channels 132 -139 0x84 - 0x8b 10000100 - 10001011 r/w registers reserved for testing channels 0-3 140 - 191 0x8c - 0xbf 10001100 - 10 111111 reserved 192 0xc0 11000000 command control register for all 8 channels 193 - 195 0xc1 - 0xc3 11000001 - 11000011 reserved 196 - 203 0xc4 - 0xcb 11000100 - 11001011 r/w registers reserved for testing channels 4-7 204 - 253 0xcc - 0xfd 11001100 - 11111101 reserved 254 0xfe 11111110 device ?id? 255 0xff 11111111 device ?revision id? t able 22: m icroprocessor r egister b it d escription r eg . # a ddress r eg . t ype b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 channel 0 control registers 0 00000000 hex 0x00 r/w qrss/prbs prbs_rx/ tx rxon_n eqc4_n eqc3_n eqc2_n eqc1_n eqc0_n 1 00000001 hex 0x01 r/w rxtsel_n txtsel_n tersel1_n tersel0_n jasel1_n jasel0_n jabw_n fifos_n 2 00000010 hex 0x02 r/w invqrss_n txtest2_n txtest1_n txtest0_n txon_n loop2_n loop1_n loop0_n 3 00000011 hex 0x03 r/w nlcde1_n nlcde0_n codes_n rxres1_n rxres0_n insbpv_n insber_n reserved 4 00000100 hex 0x04 r/w reserved dmoie_n flsie_n lcvie_n nlcdie_n aisdie_n rlosie_n qrpdie_n 5 00000101 hex 0x05 ro reserved dmo_n fls_n lcv_n nlcd_n aisd_n rlos_n qrpd_n 6 00000110 hex 0x06 rur reserved dmois_n flsis_n lcvis_n nlcdis_n aisdis_n rlosis_n qrpdis_n
xrt83vl38 55 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 7 00000111 hex 0x07 ro reserved reserved clos5_n clos4_n clos3_n clos2_n clos1_n clos0_n 8 00001000 hex 0x08 r/w x b6s1_n b5s1_n b4s1_n b3s1_n b2s1_n b1s1_n b0s1_n 9 00001001 hex 0x09 r/w x b6s2_n b5s2_n b4s2_n b3s2_n b2s2_n b1s2_n b0s2_n 10 00001010 hex 0x0a r/w x b6s3_n b5s3_n b4s3_n b3s3_n b2s3_n b1s3_n b0s3_n 11 00001011 hex 0x0b r/w x b6s4_n b5s4_n b4s4_n b3s4_n b2s4_n b1s4_n b0s4_n 12 00001100 hex 0x0c r/w x b6s5_n b5s5_n b4s5_n b3s5_n b2s5_n b1s5_n b0s5_n 13 00001101 hex 0x0d r/w x b6s6_n b5s6_n b4s6_n b3s6_n b2s6_n b1s6_n b0s6_n 14 00001110 hex 0x0e r/w x b6s7_n b5s7_n b4s7_n b3s7_n b2s7_n b1s7_n b0s7_n 15 00001111 hex 0x0f r/w x b6s8_n b5s8_n b4s8_n b3s8_n b2s8_n b1s8_n b0s8_n reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 command control global registers for all 8 channels 16-31 0001xxxx hex 0x10- 0x1f r/w channel 1control register (see r egisters 0-15 for description) 32-47 0010xxxx hex 0x20- ox2f r/w channel 2 control register (see registers 0-15 for description) 48-63 0011xxxx hex 0x30- 0x3f r/w channel 3 control register (see registers 0-15 for description) 64-79 0100xxxx hex 0x40- 0x4f r/w channel 4 control register (see registers 0-15 for description) 80-95 0101xxxx hex 0x50- 0x5f r/w channel 5 control register (see registers 0-15 for description) 96-111 0110xxxx hex 0x60- 0x6f r/w channel 6 control register (see registers 0-15 for description) 112-127 0111xxxx hex 0x70- 0x7f r/w channel 7 control register (see registers 0-15 for description) command control registers for all 8 channels 128 10000000 hex 0x80 r/w sr/ dr ataos rclke tclke datap reserved gie sreset 129 10000001 hex 0x81 r/w reserved clksel2 clksel1 clksel0 mclkrate rxmute exlos ict 130 10000010 hex 0x82 r/w txoncntl tercntl reserved reserved reserved t able 22: m icroprocessor r egister b it d escription r eg . # a ddress r eg . t ype b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
xrt83vl38 56 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 131 10000011 hex 0x83 r/w gauge1 gauge0 reserved reserved sl_1 sl_0 eqg_1 eqg_0 test registers for channels 0 - 3 132 10000100 r/w test byte 0 133 10000101 r/w test byte 1 134 10000110 r/w test byte 2 135 10000111 r/w test byte 3 136 10001000 r/w test byte 4 137 10001001 r/w test byte 5 138 10001010 r/w test byte 6 139 10001011 r/w test byte 7 unused registers 140-191 100011xx command control register for all 8 channels 192 11000000 hex 0xc0 r/w reserved reserved reserved reserved reserved reserved reserved e1arben unused registers 193-195 110000xx test registers for channels 4 - 7 196 11000100 r/w test byte 0 197 11000101 r/w test byte 0 198 11000110 r/w test byte 0 199 11000111 r/w test byte 0 200 11001000 r/w test byte 0 201 11001001 r/w test byte 0 202 11001010 r/w test byte 0 203 11001011 r/w test byte 0 unused registers 204 11001100 ?. 253 11111101 id registers 254 11111110 hex 0xfe ro device id hex: fd - binary 11101010 (0xea) 255 11111111 hex 0xff ro device ?revision id? t able 22: m icroprocessor r egister b it d escription r eg . # a ddress r eg . t ype b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
xrt83vl38 57 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator microprocessor register descriptions t able 23: m icroprocessor r egister #0, b it d escription r egister a ddress 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 qrss/prbs qrss/prbs select bit this bit selects between qrss and prbs. 1 = qrss 0 = prbs r/w 0 d6 prbs_rx/ tx prbs receive/transmit select: this bit is used to select where the output of the prbs gener - ator is directed if prbs generation is enabled. 0 = normal operation - prbs gener ator is output on ttip and tring if prbs generation is enabled. 1 = prbs generator is output on rpos; rneg is internally grounded, if prbs generation is enabled. n ote : if prbs generation is disabled (see txtest[2:0]), user should set this bit to ?0? for normal operation. r/w d5 rxon_n receiver on: writing a ?1? into this bit location turns on the receive section of channel n. writing a ?0? shuts off the receiver section of channel n. n otes : 1. this bit provides independent turn-off or turn-on control of each receiver channel. 2. in hardware mode all receiver channels are always on in the tqfp package. in the bga packace all receiver channels can be tur ned on or off together by applying the appropriate signal to the rxon pin (# k16). r/w 0 d4 eqc4_n equalizer control bit 4: this bit together with eqc[3:0] are used for controlling transmit pulse shaping, transmit line build- out (lbo) and receive monitoring for either t1 or e1 modes of operation. see table 5 for description of equalizer control bits. r/w 0 d3 eqc3_n equalizer control bit 3: see bit d4 description for function of this bit r/w 0 d2 eqc2_n equalizer control bit 2: see bit d4 description for function of this bit r/w 0
xrt83vl38 58 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 d1 eqc1_n equalizer control bit 1: see bit d4 description for function of this bit r/w 0 d0 eqc0_n equalizer control bit 0: see bit d4 description for function of this bit r/w 0 t able 23: m icroprocessor r egister #0, b it d escription
xrt83vl38 59 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 24: m icroprocessor r egister #1, b it d escription r egister a ddress 00000001 00010001 00100001 00110001 01000001 01010001 01100001 01110001 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 rxtsel_n receiver termination select: in host mode, this bit is used to select between the internal and external line termination modes for the receiver according to the following table; r/w 0 d6 txtsel_n transmit termination select: in host mode, this bit is used to select between the internal and external line termination modes for the transmitter acco rding to the following table; r/w 0 d5 tersel1_n termination impedance select1: in host mode and in internal te rmination mode, (txtsel = ?1? and rxtsel = ?1?) tersel[1:0] control the transmit and receive termination impedance according to the following table; in the internal termination mode , the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor. in the internal termination mode, the transmitter output should be ac coupled to the transformer. r/w 0 d4 tersel0_n termination impedance select bit 0: r/w 0 rxtsel rx termination 0 1 external internal txtsel tx termination 0 1 external internal tersel1 tersel0 0 0 0 1 1 0 1 1 termination 100 ? 110 ? 75 ? 120 ?
xrt83vl38 60 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 d3 jasel1_n jitter attenuator select bit 1: the jasel1 and jasel0 bits are used to disable or place the jitter attenuator of each chan - nel independently in the transmit or receive path. r/w 0 d2 jasel0_n jitter attenuator select bit 0: see description of bit d3 for the function of this bit. r/w 0 d1 jabw_n jitter attenuator bandwidth select: in e1 mode, set this bit to ?1? to select a 1.5hz bandwidth for the jitter attenuator. the fifo length will be automatically set to 64 bits. set this bit to ?0? to select 10hz bandwidth for the jitter attenuator in e1 mode. in t1 mode th e jitter attenuator bandwidth is perma - nently set to 3hz, and the state of this bit has no effect on the bandwidth. r/w 0 d0 fifos_n fifo size select: see table of bit d1 above for the function of this bit. r/w 0 t able 24: m icroprocessor r egister #1, b it d escription jasel1 bit d3 jasel0 bit d2 0 0 0 1 1 0 1 1 ja path ja disabled ja in transmit path ja in receive path ja in receive path 0 1 0 1 0 1 0 1 fifos_n bit d0 0 0 1 1 0 0 1 1 jabw bit d1 t1 t1 t1 t1 e1 e1 e1 e1 mode 32 64 32 64 32 64 64 64 fifo size 3 3 3 3 10 10 1.5 1.5 ja b-w hz
xrt83vl38 61 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 25: m icroprocessor r egister #2, b it d escription r egister a ddress 00000010 00010010 00100010 00110010 01000010 01010010 01100010 01110010 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 invqrss_n invert qrss pattern: when tqrss is active, writing a ?1? to this bit inverts the polarity of transmitted qrss pattern. writing a ?0? sends the qrss pattern with no inversion. r/w 0 d6 txtest2_n transmit test pattern bit 2 : this bit together with txtest1 and txtest0 are used to generate and transmit test patterns according to the following table: tdqrss (transmit/detect quasi-random signal): this condition when activated enables quasi-random signal source generation and detection for the selected channel number n. in a t1 system qrss pattern is a 2 20 -1 pseudo- random bit sequence (prbs) with no more than 14 consecu - tive zeros. in a e1 system, qrss is a 2 15 -1 prbs pattern. taos (transmit all ones): activating this condition enables the transmission of an all o nes pattern from the selected channel number n. tluc (transmit network loop-up code): activating this condition enables the network loop-up code of ?00001? to be transmitted to the line for the selected channel number n. when network loop-up code is being transmitted, the xrt83vl38 will ignore the automatic loop-code detection and remote loop-back activation (nlcde1 =?1?, nlcde0 =?1?, if activated) in order to avoid activating remote digital loop-back automatically when the remote terminal responds to the loop-back request. tldc (transmit network loop-down code): activating this condition enables the network loop-down code of ?001? to be transmitted to the line for the selected channel number n. r/w 0 d5 txtest1_n transmit test pattern bit 1: see description of bit d6 for the function of this bit. r/w 0 0 0 0 1 1 0 1 1 1 1 1 1 x x 0 no pattern tdqrss taos tluc test pattern tldc txtest1 txtest0 txtest2
xrt83vl38 62 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 d4 txtest0_n transmit test pattern bit 0: see description of bit d6 for the function of this bit. r/w 0 d3 txon_n transmitter on: writing a ?1? into this bit location turns on the transmit and receive sections of channel n. writing a ?0? shuts off the transmit section of channel n. in this mode, ttip_n and tring_n driver outputs will be tri-stated for power reduction or redundancy applications. r/w 0 d2 loop2_n loop-back control bit 2: this bit together with the loop1 and loop0 bits control the loop-back modes of the chip according to the following table: d1 loop1_n loop-back control bit 1: see description of bit d2 for the function of this bit. r/w 0 d0 loop0_n loop-back control bit 0: see description of bit d2 for the function of this bit. r/w 0 t able 25: m icroprocessor r egister #2, b it d escription loop2 0 1 1 1 1 loop1 x 0 0 1 1 loop0 x 0 1 0 1 loop-back mode no loop-back dual loop-back analog loop-back remote loop-back digital loop-back
xrt83vl38 63 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 26: m icroprocessor r egister #3, b it d escription r egister a ddress 00000011 00010011 00100011 00110011 01000011 01010011 01100011 01110011 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 nlcde1_n network loop code de tection enable bit 1: this bit together with nlcde0_ n control the loop-code detec - tion of each channel. when nlcde1 =?0? and nlcde0 = ?1? or nlcde1 = ?1? and nlcde0 = ?0?, the chip is manually programmed to monitor the receive data for the loop-up or loop-down code respec - tively.when the presence of the ?00001? or ?001? pattern is detected for more than 5 seconds, the status of the nlcd bit is set to ?1? and if the nlcd interrupt is enabled, an interrupt is initiated.the host has the opti on to control the loop-back function manually. setting the nlcde1 = ?1? and nlcde0 = ?1? enables the automatic loop-code detection and remote loop-back acti - vation mode. as this mode is initiated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to mon - itor the receive data for the loo p-up code. if the ?00001? pat - tern is detected for longer than 5 seconds, the nlcd bit is set ?1?, remote loop-back is activated and the chip is automati - cally programmed to monitor the receive data for the loop- down code. the nlcd bit stays set even after the chip stops receiving the loop-up code. the remote loop-back condition is removed when the chip receives the loop-down code for more than 5 seconds or if the automatic loop-code detection mode is terminated. r/w 0 d6 nlcde0_n network loop code de tection enable bit 0: see description of d7 fo r function of this bit. r/w 0 d5 codes_n encoding and decoding select: writing a ?0? to this bits selects hdb3 or b8zs encoding and decoding for channel number n. writing ?1? selects an ami coding scheme. this bit is only active when single rail mode is selected. r/w 0 nlcde1 nlcde0 0 0 0 1 1 0 1 1 function disable loop-code detection detect loop-up code in receive data detect loop-down code in receive data automatic loop-code detection
xrt83vl38 64 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 d4 rxres1_n receive external resistor control pin 1: in host mode, this bit along with the rxres0_n bit selects the value of the external receive fixed resistor according to the following table; r/w 0 d3 rxres0_n receive external resistor control pin 0: for function of this bit see description of d4 the rxres1_n bit. r/w 0 d2 insbpv_n insert bipolar violation: when this bit transitions from ?0? to ?1?, a bipolar violation is in serted in the transmitted data stream of the selected channel number n. bipolar violation can be inserted either in the qrss pattern, or input data when operating in single-rail mode. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of a bipolar violation, a ?0? should be written in this bit location before writing a ?1?. r/w 0 d1 insber_n insert bit error: with tdqrss enabled, when this bit transi - tions from ?0? to ?1?, a bit error will be inserted in the transmit - ted qrss pattern of the selected channel number n. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of bit error, a ?0? should be written in this bit location before writing a ?1?. r/w 0 d0 reserved reserved r/w 0 t able 27: m icroprocessor r egister #4, b it d escription r egister a ddress 00000100 00010100 00100100 00110100 01000100 01010100 01100100 01110100 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmoie_n dmo interrupt enable: writing a ?1? to this bit enables dmo interrupt generation, writing a ?0? masks it. r/w 0 t able 26: m icroprocessor r egister #3, b it d escription rxres1_n 0 0 required fixed external rx resistor no external fixed resistor 240 ? rxres0_n 0 1 1 1 210 ? 150 ? 0 1
xrt83vl38 65 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator d5 flsie_n fifo limit status interrupt enable: writing a ?1? to this bit enables interrupt generation when the fifo limit is within to 3 bits, writing a ?0? to masks it. r/w 0 d4 lcvie_n line code violation interrupt enable: writing a ?1? to this bit enables line code violation interrupt generation, writing a ?0? masks it. r/w 0 d3 nlcdie_n network loop-code detection interrupt enable: writing a ?1? to this bit enables network loop-code detection interrupt generation, writing a ?0? masks it. r/w 0 d2 aisdie_n ais interrupt enable: writing a ?1? to this bit enables alarm indication signal detection inte rrupt generation, writing a ?0? masks it. r/w 0 d1 rlosie_n receive loss of signal interrupt enable: writing a ?1? to this bit enables loss of receive signal interrupt generation, writing a ?0? masks it. r/w 0 d0 qrpdie_n qrss pattern detection interrupt enable: writing a ?1? to this bit enables qrss pattern de tection interrupt generation, writing a ?0? masks it. r/w 0 t able 27: m icroprocessor r egister #4, b it d escription
xrt83vl38 66 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 28: m icroprocessor r egister #5, b it d escription r egister a ddress 00000101 00010101 00100101 00110101 01000101 01010101 01100101 01110101 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmo_n driver monitor output: this bit is set to a ?1? to indicate transmit driver failure is detected . the value of this bit is based on the current status of dmo for the corresponding channel. if the dmoie bit is enabled, any transition on this bit will gener - ate an interrupt. ro 0 d5 fls_n fifo limit status: this bit is set to a ?1? to indicate that the jit - ter attenuator read/write fifo pointers are within +/- 3 bits. if the flsie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d4 lcv_n line code violation: this bit is set to a ?1? to indicate that the receiver of channel n is currently detecting a line code viola - tion or an excessive number of zeros in the b8zs or hdb3 modes. if the lcvie bit is enabled, any transition on this bit will generate an interrupt. ro 0
xrt83vl38 67 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator d3 nlcd_n network loop-code detection: this bit operates differently in the manual or the automatic network loop-code detection modes. in the manual loop-code detection mode , (nlcde1 = ?0? and nlcde0 = ?1? or nlcde1 = ?1? and nlcde0 = ?0?) this bit gets set to ?1? as soon as the loop-up (?00001?) or loop- down (?001?) code is detected in the receive data for longer than 5 seconds. the nlcd bit stays in the ?1? state for as long as the chip detects the presence of the loop-code in the receive data and it is reset to ?0 ? as soon as it stops receiving it. in this mode, if the nlcd in terrupt is enabled, the chip will initiate an interrupt on every transition of the nlcd. when the automatic loop- code detection mode, (nlcde1 = ?1? and nlcde0 =?1?) is init iated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to mon - itor the receive input data for t he loop-up code. this bit is set to a ?1? to indicate that the ne twork loop code is detected for more than 5 seconds. simultaneously the remote loop-back condition is automatically activated and the chip is pro - grammed to monitor the receive data for the network loop down code. the nlcd bit stays in the ?1? state for as long as the remote loop-back condition is in effect even if the chip stops receiving the loop-up code. remote loop-back is removed if the chip detects the ?001? pattern for longer than 5 seconds in the receive data.detecting the ?001? pattern also results in resetting the nlcd interface bit and initiating an interrupt provided the nlcd interrupt enable bit is active. when programmed in automatic detection mode, the nlcd interface bit stays ?high? fo r the entire time the remote loop-back is active and initiate an interrupt anytime the status of the nlcd bit changes. in this mode, the host can monitor the state of the nlcd bit to determine if the remote loop- back is activated. ro 0 d2 aisd_n alarm indication signal detect: this bit is set to a ?1? to indi - cate all ones signal is detected by the receiver. the value of this bit is based on the current status of alarm indication signal detector of channel n. if the aisdie bit is enabled, any transi - tion on this bit will generate an interrupt. ro 0 d1 rlos_n receive loss of signal: this bit is set to a ?1? to indicate that the receive input signal is lost. the value of this bit is based on the current status of the receive input signal of channel n. if the rlosie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d0 qrpd_n quasi-random pattern detection: this bit is set to a ?1? to indicate the receiver is current ly in synchronization with qrss pattern. the value of this bit is based on the current status of quasi-random pattern detector of channel n. if the qrpdie bit is enabled, any transition on this bit will generate an interrupt. ro 0 t able 28: m icroprocessor r egister #5, b it d escription
xrt83vl38 68 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 29: m icroprocessor r egister #6, b it d escription r egister a ddress 00000110 00010110 00100110 00110110 01000110 01010110 01100110 01110110 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmois_n driver monitor output interrupt status: this bit is set to a ?1? every time the dmo status has changed since last read. n ote : this bit is reset upon read. rur 0 d5 flsis_n fifo limit interrupt status: this bit is set to a ?1? every time when fifo limit (read/write pointer with +/- 3 bits apart) sta - tus has changed since last read. n ote : this bit is reset upon read. rur 0 d4 lcvis_n line code violation interrupt status: this bit is set to a ?1? every time when lcv status has changed since last read. n ote : this bit is reset upon read. rur 0 d3 nlcdis_n network loop-code detection interrupt status: this bit is set to a ?1? every time when nlcd status has changed since last read. n ote : this bit is reset upon read. rur 0 d2 aisdis_n ais detection in terrupt status: this bit is set to a ?1? every time when aisd status has changed since last read. n ote : this bit is reset upon read. rur 0 d1 rlosis_n receive loss of signal interrupt status: this bit is set to a ?1? every time rlos status has changed since last read. n ote : this bit is reset upon read. rur 0 d0 qrpdis_n quasi-random pattern detection interrupt status: this bit is set to a ?1? every time when qrpd status has changed since last read. n ote : this bit is reset upon read. rur 0
xrt83vl38 69 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 30: m icroprocessor r egister #7, b it d escription r egister a ddress 00000111 00010111 00100111 00110111 01000111 01010111 01100111 01110111 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 reserved ro 0 d5 clos5_n cable loss bit 5: clos[5:0]_n are the si x bit receive selec - tive equalizer setting which is also a binary word that repre - sents the cable attenuation indication within 1db. clos5_n is the most significant bit (msb) and clos0_n is the least sig - nificant bit (lsb). ro 0 d4 clos4_n cable loss bit 4: see description of d5 for function of this bit. ro 0 d3 clos3_n cable loss bit 3: see description of d5 for function of this bit. ro 0 d2 clos2_n cable loss bit 2: see description of d5 for function of this bit. ro 0 d1 clos1_n cable loss bit 1: see description of d5 for function of this bit. ro 0 d0 clos0_n cable loss bit 0: see description of d5 for function of this bit. ro 0
xrt83vl38 70 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 31: m icroprocessor r egister #8, b it d escription r egister a ddress 00001000 00011000 00101000 00111000 01001000 01011000 01101000 01111000 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s1_n - b0s1_n arbitrary transmit pulse shape, segment 1: the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time seg - ments whose combined duration is equal to one period of mclk. this 7 bit number represents t he amplitude of the nth chan - nel's arbitrary pulse during the first time segment. b6s1_n- b0s1_n is in signed magnitude format with b6s1_n as the sign bit and b0s1_n as the least significant bit (lsb). r/w 0 t able 32: m icroprocessor r egister #9, b it d escription r egister a ddress 00001001 00011001 00101001 00111001 01001001 01011001 01101001 01111001 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s2_n - b0s2_n arbitrary transmit pulse shape, segment 2 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents t he amplitude of the nth chan - nel's arbitrary pulse during the second time segment. b6s2_n- b0s2_n is in signed magnitude format with b6s2_n as the sign bit and b0s2_n as the least significant bit (lsb). r/w 0
xrt83vl38 71 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 33: m icroprocessor r egister #10, b it d escription r egister a ddress 00001010 00011010 00101010 00111010 01001010 01011010 01101010 01111010 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s3_n - b0s3_n arbitrary transmit pulse shape, segment 3 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the third time segment. b6s3_n- b0s3_n is in signed magnitude format with b6s3_n as the sign bit and b0s3_n as the least significant bit (lsb). r/w 0 t able 34: m icroprocessor r egister #11, b it d escription r egister a ddress 00001011 00011011 00101011 00111011 01001011 01011011 01101011 01111011 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s4_n - b0s4_n arbitrary transmit pulse shape, segment 4 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the fourth time segment. b6s4_n- b0s4_n is in signed magnitude format with b6s4_n as the sign bit and b0s4_n as the least significant bit (lsb). r/w 0
xrt83vl38 72 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 35: m icroprocessor r egister #12, b it d escription r egister a ddress 00001100 00011100 00101100 00111100 01001100 01011100 01101100 01111100 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s5_n - b0s5_n arbitrary transmit pulse shape, segment 5 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents t he amplitude of the nth chan - nel's arbitrary pulse during the fifth time segment. b6s5_n- b0s5_n is in signed magnitude format with b6s5_n as the sign bit and b0s5_n as the least significant bit (lsb). r/w 0 t able 36: m icroprocessor r egister #13, b it d escription r egister a ddress 00001101 00011101 00101101 00111101 01001101 01011101 01101101 01111101 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s6_n - b0s6_n arbitrary transmit pulse shape, segment 6 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents t he amplitude of the nth chan - nel's arbitrary pulse during the sixth time segment. b6s6_n- b0s6_n is in signed magnitude format with b6s6_n as the sign bit and b0s6_n as the least significant bit (lsb). r/w 0
xrt83vl38 73 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 37: m icroprocessor r egister #14, b it d escription r egister a ddress 00001110 00011110 00101110 00111110 01001110 01011110 01101110 01111110 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s7_n - b0s7_n arbitrary transmit pulse shape, segment 7 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the seventh time segment. b6s7_n-b0s7_n is in signed magnitude format with b6s7_n as the sign bit and b0s7_n as the least significant bit (lsb). r/w 0 t able 38: m icroprocessor r egister #15, b it d escription r egister a ddress 00001111 00011111 00101111 00111111 01001111 01011111 01101111 01111111 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s8_n - b0s8_n arbitrary transmit pulse shape, segment 8 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in table 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the eighth time segment. b6s8_n- b0s8_n is in signed magnitude format with b6s8_n as the sign bit and b0s8_n as the least significant bit (lsb). r/w 0
xrt83vl38 74 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 39: m icroprocessor r egister #128, b it d escription r egister a ddress 10000000 n ame f unction r egister t ype r eset v alue b it # d7 sr/ dr single-rail/dual-rail select: writing a ?1? to this bit configures all 8 channels in the xrt83vl38 to operate in the single-rail mode. writing a ?0? configures the xrt83vl38 to operate in dual-rail mode. r/w 0 d6 ataos automatic transmit all ones upon rlos: writing a ?1? to this bit enables the automatic transmission of all "ones" data to the line for the channel that detects an rlos condition. writing a ?0? disables this feature. r/w 0 d5 rclke receive clock edge: writing a ?1? to this bit selects receive output data of all channels to be updated on the negative edge of rclk. wring a ?0? selects data to be updated on the positive edge of rclk. r/w 0 d4 tclke transmit clock edge: writing a ?0? to this bit selects transmit data at tpos_n/tdata_n an d tneg_n/codes_n of all channels to be sampled on the falling edge of tclk_n. writing a ?1? selects the rising edge of the tclk_n for sam - pling. r/w 0 d3 datap data polarity: writing a ?0? to this bit selects transmit input and receive output data of all channels to be active ?high?. writing a ?1? selects an active ?low? state. r/w 0 d2 reserved 0 d1 gie global interr upt enable: writing a ?1? to this bit globally enables interrupt generation for all channels. writing a ?0? disables interrupt generation. r/w 0 d0 sreset software reset ? p registers: writing a ?1? to this bit longer than 10s initiates a device reset through the microprocessor interface. all internal circuits are placed in the reset state with this bit set to a ?1? except th e microprocessor register bits. r/w 0
xrt83vl38 75 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator clock select register the input clock source is used to generate all the ne cessary clock references internally to the liu. the microprocessor timing is derived from a pll output whic h is chosen by programming the clock select bits and the master clock rate in register 0x81h. therefore, if the clock selection bits or the mclrate bit are being programmed, the frequ ency of the pll output will be ad justed accordingly. during this adjustment, it is important to "not" write to any other bit location within the same register while sele cting the input/output clock frequency. for best results, register 0x81h can be br oken down into two sub-register s with the msb being bits d[7:3] and the lsb being bi ts d[2:0] as shown in figure 31 . note: bit d[7] is a reserved bit. f igure 31. r egister 0 x 81 h s ub r egisters programming examples: example 1: changing bits d[7:3] if bits d[7:3] are the only values wit hin the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 2: changing bits d[2:0] if bits d[2:0] are the only values wit hin the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 3: changing bits within the msb and lsb in this scenario, one must initiate two write operations such that th e msb and lsb do not change within one write cycle. it is recommended that th e msb and lsb be treated as two in dependent sub-registers. one can either change the clock selection (msb) and then change bits d[2:0] (lsb) on the second write, or vice- versa. no order or sequence is necessary. t able 40: m icroprocessor r egister #129, b it d escription r egister a ddress 10000001 n ame f unction r egister t ype r eset v alue b it # d7 reserved r/w 0 d0 d1 d2 d3 d4 d5 d6 d7 msb lsb clock selection bits exlos, ict
xrt83vl38 76 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 d6 clksel2 clock select inputs for master clock synthesizer bit 2: in host mode, clksel[2:0] are inpu t signals to a programma - ble frequency synthesizer that can be used to generate a mas - ter clock from an external accura te clock source according to the following table; in hardware mode, the state of these signals are ignored and the master frequency pll is controlled by the corresponding hardware pins. r/w 0 d5 clksel1 clock select inputs for master clock synthesizer bit 1: see description of bit d6 for function of this bit. r/w 0 d4 clksel0 clock select inputs for master clock synthesizer bit 0: see description of bit d6 for function of this bit. r/w 0 d3 mclkrate master clock rate select: the state of this bit programs the master clock synthesizer to generate the t1/j1 or e1 clock. the master clock synthesizer w ill generate the e1 clock when mclkrate = ?0?, and the t1/j1 clock when mclkrate = ?1?. r/w 0 d2 rxmute receive output mute: writing a ?1? to this bit, mutes receive outputs at rpos/rdata and rneg/lcv pins to a ?0? state for any channel that detects an rlos condition. n ote : rclk is not muted. r/w 0 d1 exlos extended los: writing a ?1? to this bit extends the number of zeros at the receive input of each channel before rlos is declared to 4096 bits. writing a ?0? reverts to the normal mode (175+75 bits for t1 and 32 bits for e1). r/w 0 d0 ict in-circuit-testing: writing a ?1? to this bit configures all the output pins of the chip in high impedance mode for in-circuit- testing. setting the ict bit to ?1? is equivalent to connecting the hardware ict pin 88 to ground. r/w 0 t able 41: m icroprocessor r egister #130, b it d escription r egister a ddress 10000010 n ame f unction r egister t ype r eset v alue b it # d7 txoncntl transmit on control: in host mode, setting this bit to ?1? transfers the control of the transmit on/off function to the txon_n hardware control pins. n ote : this provides a faster on/off capability for redundancy application. r/w 0 t able 40: m icroprocessor r egister #129, b it d escription 2048 2048 2048 1544 mclke1 khz 2048 2048 1544 1544 mclkt1 khz 1544 1544 2048 1544 2048 clkout khz 1544 2048 1544 0 0 1 1 clksel0 0 0 0 0 clksel1 0 0 0 0 clksel 2 0 1 0 0 0 0 1544 2048 0 1 0 1 mclkrate 1 0
xrt83vl38 77 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator d6 tercntl termination control. in host mode, setting this bit to ?1? transfers the control of the rxtsel to the rxtsel hardware control pin. n ote : this provides a faster on/off capability for redundancy application. r/w 0 d5-d0 reserved t able 42: m icroprocessor r egister #131, b it d escription r egister a ddress 10000011 n ame f unction r egister t ype r eset v alue b it # d7 gauge1 wire gauge selector bit 1: this bit together with bit d6 are used to select wire gauge size as shown in the table below. r/w 0 d6 gauge0 wire gauge selector bit 0: see bit d7. r/w 0 d5 txsync(sect 13) g.703 section 13 transmit pulse when this bit is set to ?1?, the liu transmitter will send the e1 synchrnonous waveform as described in section 13 of itu-t g.703. this register bit takes priority over every other liu set - ting on the transmit path. 0 = normal e1 pulse 1 = section 13 synchronous pulse r/w 0 d4 rxsync(sect 13) g.703 section 13 receiver when this bit is set to ?1?, the cdr block of the receiver is con - figured to accept a waveform as described in section 13 of itu-t g.703. 0 = normal e1 (equalizer bit settings - eqc[4:0]) 1 = section 13 synchronous pulse r/w 0 t able 41: m icroprocessor r egister #130, b it d escription gauge1 0 1 1 0 gauge0 0 1 0 1 wire size 22 and 24 gauge 26 gauge 24 gauge 22 gauge
xrt83vl38 78 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 d3 sl_1 slicer level control bit 1: this bit and bit d2 control the slic - ing level for the slicer per the following table. r/w 0 d2 sl_0 slicer level control bit 0: see description bit d3. r/w 0 d1 eqg_1 equalizer gain control bit 1: this bit together with bit d0 control the gain of the equalizer as shown in the table below. r/w 0 d0 eqg_0 equalizer gain control bit 0: see description of bit d1 r/w 0 t able 43: m icroprocessor r egister #192, b it d escription r egister a ddress 11000000 n ame f unction r egister t ype r eset v alue b it # d[7:1] reserved these register bits are not used. r/w 0 d0 e1arben e1 arbitrary pulse enable this bit is used to enable the arbitrary pulse generators for shaping the transmit pulse shape when e1 mode is selected. if this bit is set to "1", all 8 channels will be configured for the arbitrary mode. however, each channel is individually con - trolled by programming the channel registers 0xn8 through 0xnf, where n is the number of the channel. "0" = disabled (normal e1 pulse shape itu g.703) "1" = arbitrary pulse enabled r/w 0 t able 42: m icroprocessor r egister #131, b it d escription sl_1 sl_0 0 0 0 1 1 0 1 1 slicer mode normal decrease by 5% from normal increase by 5% from normal normal eqg_1 eqg_0 0 0 0 1 1 0 1 1 equalizer gain normal reduce gain by 1 db reduce gain by 3 db normal
xrt83vl38 79 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator electrical characteristics t able 44: a bsolute m aximum r atings storage temperature...................-65c to + 150c operating temperature.............-40c to + 85c supply voltage..........................-0.5v to + 3.8v v in .................................................-0.5v to + 5.5v maximum junction temperature..................................125oc theta ja......................................................................24oc/w theta jc......................................................................10oc/w t able 45: dc d igital i nput and o utput e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits power supply voltage vdd 3.13 3.3 3.46 v power supply current idd 325 400 475 ma input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage @ ioh = 2.0ma v oh 2.4 - - v output low voltage @iol = 2ma. v ol - - 0.4 v input leakage current (except input pins with pull-up or pull- down resistor). i l - - 10 ? a input capacitance c i - 5.0 - pf output load capacitance c l - - 25 pf t able 46: xrt83vl38 p ower c onsumption vdd=3.3v5%, t a =25c, unless otherwise specified m ode s upply v oltage i mpedance termination r esistor t ransformer r atio t yp . m ax . u nit t est c onditions r eceiver t ransmitter e1 3.3v 75 ? internal 1:1 1:2 1.96 2.16 w 100% ?1?s? e1 3.3v 120 ? internal 1:1 1:2 1.85 2.04 w 100% ?1?s? t1 3.3v 100 ? internal 1:1 1:2 1.95 2.15 w 100% ?1?s? --- 3.3v --- external --- --- 429 472 mw all transmitters off
xrt83vl38 80 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 47: e1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 10 15 12.5 175 20 255 db db cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? applica - tion. with -18db interference signal added. receiver sensitivity (long haul with cable loss) nominal extended 0 0 36 43 db db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? applica - tion. with -18db interference signal added. input impedance 13 k ? input jitter tolerance: 1 hz 10khz-100khz 37 0.2 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 36 -0.5 khz db itu g.736 jitter attenuator corner fre - quency (-3db curve) (jabw=0) (jabw=1) - 10 1.5 - hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 - - db db db itu-g.703
xrt83vl38 81 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 48: t1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 100 15 12.5 175 20 - 250 - - db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - db with nominal pulse amplitude of 3.0v for 100 ? termination receiver sensitivity (long haul with cable loss) 0 - 36 db with nominal pulse amplitude of 3.0v for 100 ? termination input impedance 13 - k ? jitter tolerance: 1hz 10khz - 100khz 138 0.4 - - - - uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 9.8 - 0.1 khz db tr-tsy-000499 jitter attenuator corner fre - quency (-3db curve) - 6 -hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 20 25 25 - - - db db db t able 49: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss g.703/ch-ptt ets 300166 51-102khz 8db 6db 102-2048khz 14db 8db 2048-3072khz 10db 8db
xrt83vl38 82 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 50: e1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 75 ? application 120 ? application 2.185 2.76 2.37 3.00 2.555 3.24 v v transformer with 1:2 ratio and internal termination. output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 jitter added by the transmitter out - put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 8 14 10 - - - - - - db db db etsi 300 166, chptt t able 51: t1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 2.5 3.0 3.50 v transformer with 1:2 ratio and and internal termination. output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance - - + 200 mv ansi t1.102 jitter added by the transmitter out - put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 15 15 15 - - - db db db
xrt83vl38 83 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator f igure 32. itu g.703 p ulse t emplate t able 52: t ransmit p ulse m ask s pecification test load impedance 75 ? resistive (coax) 120 ? resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note ? v corresponds to the nominal peak value. 20% 20%
xrt83vl38 84 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 f igure 33. itu g.703 s ection 13 s ynchronous i nterface p ulse t emplate t able 53: e1 s ynchronous i nterface t ransmit p ulse m ask s pecification test load impedance 75 ? resistive (coax) 120 ? resistive (twisted pair) maximum peak voltage of a mark 1.5v 1.9v minimum peak voltage of a mark 0.75v 1.0v nominal pulse width 244ns 244ns t 30 t 4 t 4 t 4 t 4 t +v +v 1 ?v 0 t1818900-92 ?v 1 t 30 t 30 t 30 t 30 t 30 shaded area in which signal should be monotonic t average period of synchronizing signal
xrt83vl38 85 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator f igure 34. dsx-1 p ulse t emplate ( normalized amplitude ) t able 54: dsx1 i nterface i solated pulse mask and corner points m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v
xrt83vl38 86 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 55: ac e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits e1 mclk clock frequency - 2.048 mhz t1 mclk clock frequency - 1.544 mhz mclk clock duty cycle 40 - 60 % mclk clock tolerance - 50 - ppm tclk duty cycle t cdu 30 50 70 % transmit data setup time t su 50 - - ns transmit data hold time t ho 30 - - ns tclk rise time(10%/90%) tclk r - - 40 ns tclk fall time(90%/10%) tclk f - - 40 ns rclk duty cycle r cdu 45 50 55 % receive data setup time r su 150 - - ns receive data hold time r ho 150 - - ns rclk to data delay rdy - - 40 ns rclk rise time(10% to 90%) with 25pf loading. rclk r - - 40 ns rclk fall time(90% to 10%) with 25pf loading. rclk f 40 ns f igure 35. t ransmit c lock and i nput d ata t iming tclk r tclk f tclk tpos/tdata or tneg t su t ho
xrt83vl38 87 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator microprocessor interface i/o timing i ntel i nterface t iming - a synchronous the signals used for the intel microprocessor interfac e are: address latch enable (ale), read enable ( rd ), write enable ( wr ), chip select ( cs ), address and data bits. the microprocessor interface uses minimum ex - ternal glue logic and is compatible with the timings of the 8051 or 80c188 with an 8-16 mhz clock frequency, and with the timings of x86 or i960 family or microprocessors. the interface timing shown in figure 37 and figure 39 is described in table 56 . f igure 36. r eceive c lock and o utput d ata t iming f igure 37. i ntel a synchronous p rogrammed i/o i nterface t iming rclk r rclk f rclk rpos or rneg r dy r ho addr[6:0] data[7:0] rd_ds wr_r/w rdy_dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 3 t 2 t 4 valid address valid address t 5 t 5 ale_as cs
xrt83vl38 88 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 t able 56: a synchronous m ode 1 - i ntel 8051 and 80188 i nterface t iming s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 20 - ns t 2 rd assert to rdy assert - 135 ns na rd pulse width (t2) 135 - ns t 3 cs falling edge to wr assert 20 - ns t 4 wr assert to rdy assert - 135 ns na wr pulse width (t2) 135 - ns t 5 cs falling edge to as falling edge 0 - ns reset pulse width - both motorola and intel operations (see figure 39 ) t 9 reset pulse width 10 s
xrt83vl38 89 rev. 1.0.1 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator m otorola a sychronous i nterface t iming the signals used in the motorola microprocessor interface mode are: address strobe (as), data strobe ( ds ), read/write enable (r/ w ), chip select ( cs ), address and data bits. the interface is compatible with the timing of a motorola 68000 microprocessor family with up to 16.67 mhz clock frequency. the interface timing is shown in figure 38 and figure 39 . the i/o specifications are shown in table 57 . f igure 38. m otorola 68k a synchronous p rogrammed i/o i nterface t iming t able 57: a synchronous - m otorola 68k - i nterface t iming s pecification s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds assert 20 - ns t 2 ds assert to dtack assert - 135 ns na ds pulse width (t2) 135 - ns t 3 cs falling edge to as falling edge 0 - ns reset pulse width - both motoro la and intel operations (see figure 39 ) t 9 reset pulse width 10 s f igure 39. m icroprocessor i nterface t iming - r eset p ulse w idth cs addr[6:0] data[7:0] rd_ds wr_r/w rdy_dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 valid address valid address t 3 t 3 t 1 t 2 ale_as reset t 9
xrt83vl38 90 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 package dimensions 225 ball plastic ball grid array (bottom view) (19.0 x 19.0 x 1.0mm) 1 2 4 3 7 86 5 17 16 14 15 12 13 11 10 9 18 a b c d e f g h j k l m n p r t u v d d1 d d1 a1 feature / mark d2 a a1 a2 a3 e b (a1 corner feature is mfger option) seating plane symbol min max min max a 0.049 0.096 1.24 2.45 a1 0.016 0.024 0.40 0.60 a2 0.013 0.024 0.32 0.60 a3 0.020 0.048 0.52 1.22 d 0.740 0.756 18.80 19.20 d1 0.669 bsc 17.00 bsc d2 0.665 0.669 16.90 17.00 b 0.020 0.028 0.50 0.70 e 0.039 bsc 1.00 bsc inches millimeters note: the control dimension is in millimeter.
91 notice exar corporation and the exar corporation logo are trademarks of exar corporation. the information contained herein is the property to exar corporation and is strict ly confidential. except as expressly authoriz ed in writing by exar corporation, the holder shall keep all information herein confidential, shall disclose it only to its employees with a need to know, and shall p rotect it, in whole or in part, from disclosure and dissemination to third parties with the same degree of care it uses to protect its own confidential information, but with no less reasonable care. exc ept as expressly authorized in writing by exar corporation, the holder is granted no rights to use the information herein. the information found in this document is subject to change without notice and exar corporation reserves the right to make changes to the products contained in this publication. the material is provided on an "as is" basis. exar corporation assumes n o responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement , neither does it convey any license under its patent rights, copyrights, or trade secrets, nor the rights of others. char ts and schedules contained here in are only for illustration purpos es and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in lif e support applications where the failure or malfunction of the pr oduct can reasonably be expected to cause failure of the life su pport system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications. copyright 2010 exar corporation datasheet august 2010. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. xrt83vl38 octal t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 ordering information p art n umber p ackage o perating t emperature r ange XRT83VL38IB 225 ball bga -40 c to +85 c revisions r evision # d ate d escription 1.0.0 6/15/09 first release of the released datasheet 1.0.1 8/27/10 added missing pin definitions to the pin description table and updated micro-p documentation in functional desription section.

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